[llvm] [RISCV] Add option to disable ASM compress. (PR #131670)

[Sam Elliott via llvm-commits]

lenary wrote:

> > Why do you need this as an option? There is no explanation in the PR.
> 
> Sure - it is needed for testing.

In LLVM, or in e.g. external projects? If only the former, we can land this, under the understanding we can remove it when exact mode lands, which I'm aiming to be before 21.0.

> 
> > You can currently use `.option norvc`, and I'm working on a new option for an "exact" mode.
> 
> The only limitation with this option that we can not put compressed instruction between the:
> 
> ```
> .option push
> .option norvc
>     // ...
> .option pop
> ```
> 
> Could live with that by wrapping all non compressed instructions, but that would increase the verbosity of the assembly source.
> 
> What would the option for "exact" mode do? Does it guarantee that something written as a non-compressed instruction in assembly, stays as a non-compressed instruction all the way down to the binary, event when targeting the C extension?

I wrote a proposal here, which hasn't been accepted yet but seems to have broad consensus for the main parts (disabling compression and both branch and linker relaxation) https://github.com/riscv-non-isa/riscv-asm-manual/pull/122

And I have an in-progress PR here which I need to get back to to sort out disabling linker relaxations, hopefully this week: https://github.com/llvm/llvm-project/pull/122483

I believe it covers your use-cases. The reason it also disables linker relaxation is to provide a better end-to-end guarantee which toolchain users (e.g. DV engineers trying to test a chip or simulator) can take advantage of.

https://github.com/llvm/llvm-project/pull/131670