[llvm] [RISCV] Support .option {no}exact (PR #122483)
Sam Elliott via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 19 13:52:06 PDT 2025
https://github.com/lenary updated https://github.com/llvm/llvm-project/pull/122483
>From 8d8ed46fbeec95c2840c612f64dbc65fb98b3f8f Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Fri, 10 Jan 2025 08:02:07 -0800
Subject: [PATCH 1/3] [RISCV] Support .option (no)autocompress
This is the implementation of a new assembler-only option to allow the
automatic compression of RISC-V instructions to be switched off without
changing the currently enabled architectural features.
This allows users better control over the autocompression feature of the
assembler, so they can get the exact instructions they want.
This will become more useful as the following things happen:
- `.option norvc` is deprecated/removed (which is sometimes used for
this purpose).
- Extensions are added where the destination instruction cannot be
disabled separately to the source instruction, either because the
destination is in the base architecture, or because it is in the same
extension as the source.
- Extensions wider than 32-bits are added, which make CompressPats more
complex to use intuitively, especially if the destination is a 32-bit
instruction.
---
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 28 +++++++-
.../RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 2 +
.../RISCV/MCTargetDesc/RISCVELFStreamer.h | 2 +
.../MCTargetDesc/RISCVTargetStreamer.cpp | 10 +++
.../RISCV/MCTargetDesc/RISCVTargetStreamer.h | 4 ++
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 4 +-
llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++
llvm/test/MC/RISCV/option-autocompress.s | 70 +++++++++++++++++++
8 files changed, 122 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/MC/RISCV/option-autocompress.s
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 2205c67c2d21b..18794ed3b7fbf 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3064,6 +3064,8 @@ bool RISCVAsmParser::parseDirectiveOption() {
getTargetStreamer().emitDirectiveOptionRVC();
setFeatureBits(RISCV::FeatureStdExtC, "c");
+ clearFeatureBits(RISCV::FeatureDisableAsmCompression,
+ "disable-asm-compression");
return false;
}
@@ -3074,6 +3076,28 @@ bool RISCVAsmParser::parseDirectiveOption() {
getTargetStreamer().emitDirectiveOptionNoRVC();
clearFeatureBits(RISCV::FeatureStdExtC, "c");
clearFeatureBits(RISCV::FeatureStdExtZca, "zca");
+ setFeatureBits(RISCV::FeatureDisableAsmCompression,
+ "disable-asm-compression");
+ return false;
+ }
+
+ if (Option == "autocompress") {
+ if (Parser.parseEOL())
+ return true;
+
+ getTargetStreamer().emitDirectiveOptionAutoCompress();
+ clearFeatureBits(RISCV::FeatureDisableAsmCompression,
+ "disable-asm-compression");
+ return false;
+ }
+
+ if (Option == "noautocompress") {
+ if (Parser.parseEOL())
+ return true;
+
+ getTargetStreamer().emitDirectiveOptionNoAutoCompress();
+ setFeatureBits(RISCV::FeatureDisableAsmCompression,
+ "disable-asm-compression");
return false;
}
@@ -3326,7 +3350,9 @@ bool RISCVAsmParser::parseDirectiveVariantCC() {
void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
MCInst CInst;
- bool Res = RISCVRVC::compress(CInst, Inst, getSTI());
+ bool Res = false;
+ if (!getSTI().hasFeature(RISCV::FeatureDisableAsmCompression))
+ Res = RISCVRVC::compress(CInst, Inst, getSTI());
if (Res)
++RISCVNumInstrsCompressed;
S.emitInstruction((Res ? CInst : Inst), getSTI());
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index ea0e9fcde21cf..218e0078999f3 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -53,6 +53,8 @@ void RISCVTargetELFStreamer::emitDirectiveOptionPIC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoPIC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionRVC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoRVC() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionAutoCompress() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionNoAutoCompress() {}
void RISCVTargetELFStreamer::emitDirectiveOptionRelax() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoRelax() {}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
index 47df31af3057d..33acf5828f9f4 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
@@ -62,6 +62,8 @@ class RISCVTargetELFStreamer : public RISCVTargetStreamer {
void emitDirectiveOptionNoPIC() override;
void emitDirectiveOptionRVC() override;
void emitDirectiveOptionNoRVC() override;
+ void emitDirectiveOptionAutoCompress() override;
+ void emitDirectiveOptionNoAutoCompress() override;
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
void emitDirectiveVariantCC(MCSymbol &Symbol) override;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index 99f57f47835ab..1e33633d1169b 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -39,6 +39,8 @@ void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
+void RISCVTargetStreamer::emitDirectiveOptionAutoCompress() {}
+void RISCVTargetStreamer::emitDirectiveOptionNoAutoCompress() {}
void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
void RISCVTargetStreamer::emitDirectiveOptionArch(
@@ -122,6 +124,14 @@ void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {
OS << "\t.option\tnorvc\n";
}
+void RISCVTargetAsmStreamer::emitDirectiveOptionAutoCompress() {
+ OS << "\t.option\tautocompress\n";
+}
+
+void RISCVTargetAsmStreamer::emitDirectiveOptionNoAutoCompress() {
+ OS << "\t.option\tnoautocompress\n";
+}
+
void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
OS << "\t.option\trelax\n";
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
index cb8bc21cb6355..33ab55ca85536 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
@@ -47,6 +47,8 @@ class RISCVTargetStreamer : public MCTargetStreamer {
virtual void emitDirectiveOptionNoPIC();
virtual void emitDirectiveOptionRVC();
virtual void emitDirectiveOptionNoRVC();
+ virtual void emitDirectiveOptionAutoCompress();
+ virtual void emitDirectiveOptionNoAutoCompress();
virtual void emitDirectiveOptionRelax();
virtual void emitDirectiveOptionNoRelax();
virtual void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args);
@@ -84,6 +86,8 @@ class RISCVTargetAsmStreamer : public RISCVTargetStreamer {
void emitDirectiveOptionNoPIC() override;
void emitDirectiveOptionRVC() override;
void emitDirectiveOptionNoRVC() override;
+ void emitDirectiveOptionAutoCompress() override;
+ void emitDirectiveOptionNoAutoCompress() override;
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args) override;
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index b1990409754b0..d5de046b96053 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -254,7 +254,9 @@ void RISCVAsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
bool RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst,
const MCSubtargetInfo &SubtargetInfo) {
MCInst CInst;
- bool Res = RISCVRVC::compress(CInst, Inst, SubtargetInfo);
+ bool Res = false;
+ if (!SubtargetInfo.hasFeature(RISCV::FeatureDisableAsmCompression))
+ Res = RISCVRVC::compress(CInst, Inst, SubtargetInfo);
if (Res)
++RISCVNumInstrsCompressed;
S.emitInstruction(Res ? CInst : Inst, SubtargetInfo);
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 01bc5387e672e..a4bf4f92de27f 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1326,6 +1326,10 @@ def FeatureRelax
: SubtargetFeature<"relax", "EnableLinkerRelax", "true",
"Enable Linker relaxation.">;
+def FeatureDisableAsmCompression
+ : SubtargetFeature<"disable-asm-compression", "EnableAsmCompression", "false",
+ "Disable Automatic Assembly Compression.">;
+
foreach i = {1-31} in
def FeatureReserveX#i :
SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
diff --git a/llvm/test/MC/RISCV/option-autocompress.s b/llvm/test/MC/RISCV/option-autocompress.s
new file mode 100644
index 0000000000000..ac58a4320b259
--- /dev/null
+++ b/llvm/test/MC/RISCV/option-autocompress.s
@@ -0,0 +1,70 @@
+# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c < %s \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c \
+# RUN: -M no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c < %s \
+# RUN: | llvm-objdump --triple=riscv32 --mattr=+c --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c < %s \
+# RUN: | llvm-objdump --triple=riscv32 --mattr=+c --no-print-imm-hex -d -M no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
+
+# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c < %s \
+# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c \
+# RUN: -M no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c < %s \
+# RUN: | llvm-objdump --triple=riscv64 --mattr=+c --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c < %s \
+# RUN: | llvm-objdump --triple=riscv64 --mattr=+c --no-print-imm-hex -d -M no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
+
+
+# `.option (no)autocompress` enables and disables instruction compression in the
+# assembler, without changing the current architecture.
+#
+# The default is as if `.option autocompress` has been specified, that is, the
+# assembler compresses by default.
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+lw a0, 0(a0)
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+c.lw a0, 0(a0)
+
+# CHECK: .option noautocompress
+.option noautocompress
+
+# CHECK-BYTES: 00052503
+# CHECK-INST: lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x03,0x25,0x05,0x00]
+lw a0, 0(a0)
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+c.lw a0, 0(a0)
+
+# CHECK: .option autocompress
+.option autocompress
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+lw a0, 0(a0)
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+c.lw a0, 0(a0)
>From eba37b26f3bb88548ffcf428240c11c2370b2eae Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Mon, 13 Jan 2025 05:44:53 -0800
Subject: [PATCH 2/3] fixup! [RISCV] Support .option (no)autocompress
---
llvm/test/MC/RISCV/option-autocompress.s | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/llvm/test/MC/RISCV/option-autocompress.s b/llvm/test/MC/RISCV/option-autocompress.s
index ac58a4320b259..d394f69af0b8a 100644
--- a/llvm/test/MC/RISCV/option-autocompress.s
+++ b/llvm/test/MC/RISCV/option-autocompress.s
@@ -1,22 +1,22 @@
-# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c < %s \
+# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c %s \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c \
-# RUN: -M no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c < %s \
+# RUN: -M no-aliases %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c %s \
# RUN: | llvm-objdump --triple=riscv32 --mattr=+c --no-print-imm-hex -d - \
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c < %s \
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c %s \
# RUN: | llvm-objdump --triple=riscv32 --mattr=+c --no-print-imm-hex -d -M no-aliases - \
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
-# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c < %s \
+# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c %s \
# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c \
-# RUN: -M no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s
-# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c < %s \
+# RUN: -M no-aliases %s | FileCheck -check-prefixes=CHECK-INST %s
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c %s \
# RUN: | llvm-objdump --triple=riscv64 --mattr=+c --no-print-imm-hex -d - \
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c < %s \
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c %s \
# RUN: | llvm-objdump --triple=riscv64 --mattr=+c --no-print-imm-hex -d -M no-aliases - \
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
>From c70f679f3285a20b929906e78b3ab31e0a6caadb Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Wed, 19 Mar 2025 13:51:43 -0700
Subject: [PATCH 3/3] Update implementation to match proposal
---
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 47 ++++++------
.../RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 10 +++
.../RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 4 +-
.../RISCV/MCTargetDesc/RISCVELFStreamer.h | 4 +-
.../MCTargetDesc/RISCVTargetStreamer.cpp | 12 +--
.../RISCV/MCTargetDesc/RISCVTargetStreamer.h | 8 +-
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVFeatures.td | 6 +-
...ocompress.s => option-exact-compression.s} | 20 ++---
llvm/test/MC/RISCV/option-exact-relaxation.s | 74 +++++++++++++++++++
10 files changed, 136 insertions(+), 51 deletions(-)
rename llvm/test/MC/RISCV/{option-autocompress.s => option-exact-compression.s} (82%)
create mode 100644 llvm/test/MC/RISCV/option-exact-relaxation.s
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 4989368663b48..a7c2f563536ef 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3173,46 +3173,44 @@ bool RISCVAsmParser::parseDirectiveOption() {
return false;
}
- if (Option == "rvc") {
+ if (Option == "exact") {
if (Parser.parseEOL())
return true;
- getTargetStreamer().emitDirectiveOptionRVC();
- setFeatureBits(RISCV::FeatureStdExtC, "c");
- clearFeatureBits(RISCV::FeatureDisableAsmCompression,
- "disable-asm-compression");
+ getTargetStreamer().emitDirectiveOptionExact();
+ setFeatureBits(RISCV::FeatureExactAssembly,
+ "exact-asm");
+ clearFeatureBits(RISCV::FeatureRelax, "relax");
return false;
}
- if (Option == "norvc") {
+ if (Option == "noexact") {
if (Parser.parseEOL())
return true;
- getTargetStreamer().emitDirectiveOptionNoRVC();
- clearFeatureBits(RISCV::FeatureStdExtC, "c");
- clearFeatureBits(RISCV::FeatureStdExtZca, "zca");
- setFeatureBits(RISCV::FeatureDisableAsmCompression,
- "disable-asm-compression");
+ getTargetStreamer().emitDirectiveOptionNoExact();
+ clearFeatureBits(RISCV::FeatureExactAssembly,
+ "exact-asm");
+ setFeatureBits(RISCV::FeatureRelax, "relax");
return false;
}
- if (Option == "autocompress") {
+ if (Option == "rvc") {
if (Parser.parseEOL())
return true;
- getTargetStreamer().emitDirectiveOptionAutoCompress();
- clearFeatureBits(RISCV::FeatureDisableAsmCompression,
- "disable-asm-compression");
+ getTargetStreamer().emitDirectiveOptionRVC();
+ setFeatureBits(RISCV::FeatureStdExtC, "c");
return false;
}
- if (Option == "noautocompress") {
+ if (Option == "norvc") {
if (Parser.parseEOL())
return true;
- getTargetStreamer().emitDirectiveOptionNoAutoCompress();
- setFeatureBits(RISCV::FeatureDisableAsmCompression,
- "disable-asm-compression");
+ getTargetStreamer().emitDirectiveOptionNoRVC();
+ clearFeatureBits(RISCV::FeatureStdExtC, "c");
+ clearFeatureBits(RISCV::FeatureStdExtZca, "zca");
return false;
}
@@ -3254,8 +3252,8 @@ bool RISCVAsmParser::parseDirectiveOption() {
// Unknown option.
Warning(Parser.getTok().getLoc(), "unknown option, expected 'push', 'pop', "
- "'rvc', 'norvc', 'arch', 'relax' or "
- "'norelax'");
+ "'rvc', 'norvc', 'arch', 'relax', 'norelax', "
+ "'exact' or 'noexact'");
Parser.eatToEndOfStatement();
return false;
}
@@ -3466,11 +3464,12 @@ bool RISCVAsmParser::parseDirectiveVariantCC() {
void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
MCInst CInst;
bool Res = false;
- if (!getSTI().hasFeature(RISCV::FeatureDisableAsmCompression))
- Res = RISCVRVC::compress(CInst, Inst, getSTI());
+ const MCSubtargetInfo &STI = getSTI();
+ if (!STI.hasFeature(RISCV::FeatureExactAssembly))
+ Res = RISCVRVC::compress(CInst, Inst, STI);
if (Res)
++RISCVNumInstrsCompressed;
- S.emitInstruction((Res ? CInst : Inst), getSTI());
+ S.emitInstruction((Res ? CInst : Inst), STI);
}
void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index e752b0ec5f58c..83e6f7169e957 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -344,6 +344,10 @@ std::pair<bool, bool> RISCVAsmBackend::relaxLEB128(const MCAssembler &Asm,
// Given a compressed control flow instruction this function returns
// the expanded instruction.
unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
+ // Disable relaxation if FeatureExactAssembly
+ if (STI.hasFeature(RISCV::FeatureExactAssembly))
+ return Op;
+
switch (Op) {
default:
return Op;
@@ -371,6 +375,12 @@ unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,
const MCSubtargetInfo &STI) const {
+ // This function has access to two STIs, the member of the AsmBackend, and the
+ // one passed as an argument. The latter is more specific, so we query it for
+ // specific features.
+ if (STI.hasFeature(RISCV::FeatureExactAssembly))
+ return false;
+
return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index 0edaf8886402f..1814ca2a077f3 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -53,8 +53,8 @@ void RISCVTargetELFStreamer::emitDirectiveOptionPIC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoPIC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionRVC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoRVC() {}
-void RISCVTargetELFStreamer::emitDirectiveOptionAutoCompress() {}
-void RISCVTargetELFStreamer::emitDirectiveOptionNoAutoCompress() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionExact() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionNoExact() {}
void RISCVTargetELFStreamer::emitDirectiveOptionRelax() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoRelax() {}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
index c7cf28e00e73e..bf84f8e700e6d 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
@@ -62,8 +62,8 @@ class RISCVTargetELFStreamer : public RISCVTargetStreamer {
void emitDirectiveOptionNoPIC() override;
void emitDirectiveOptionRVC() override;
void emitDirectiveOptionNoRVC() override;
- void emitDirectiveOptionAutoCompress() override;
- void emitDirectiveOptionNoAutoCompress() override;
+ void emitDirectiveOptionExact() override;
+ void emitDirectiveOptionNoExact() override;
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
void emitDirectiveVariantCC(MCSymbol &Symbol) override;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index 0bfb832b65415..04a0feb98eec2 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -39,8 +39,8 @@ void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
-void RISCVTargetStreamer::emitDirectiveOptionAutoCompress() {}
-void RISCVTargetStreamer::emitDirectiveOptionNoAutoCompress() {}
+void RISCVTargetStreamer::emitDirectiveOptionExact() {}
+void RISCVTargetStreamer::emitDirectiveOptionNoExact() {}
void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
void RISCVTargetStreamer::emitDirectiveOptionArch(
@@ -127,12 +127,12 @@ void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {
OS << "\t.option\tnorvc\n";
}
-void RISCVTargetAsmStreamer::emitDirectiveOptionAutoCompress() {
- OS << "\t.option\tautocompress\n";
+void RISCVTargetAsmStreamer::emitDirectiveOptionExact() {
+ OS << "\t.option\texact\n";
}
-void RISCVTargetAsmStreamer::emitDirectiveOptionNoAutoCompress() {
- OS << "\t.option\tnoautocompress\n";
+void RISCVTargetAsmStreamer::emitDirectiveOptionNoExact() {
+ OS << "\t.option\tnoexact\n";
}
void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
index 33ab55ca85536..a23ac19c0cabb 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
@@ -47,8 +47,8 @@ class RISCVTargetStreamer : public MCTargetStreamer {
virtual void emitDirectiveOptionNoPIC();
virtual void emitDirectiveOptionRVC();
virtual void emitDirectiveOptionNoRVC();
- virtual void emitDirectiveOptionAutoCompress();
- virtual void emitDirectiveOptionNoAutoCompress();
+ virtual void emitDirectiveOptionExact();
+ virtual void emitDirectiveOptionNoExact();
virtual void emitDirectiveOptionRelax();
virtual void emitDirectiveOptionNoRelax();
virtual void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args);
@@ -86,8 +86,8 @@ class RISCVTargetAsmStreamer : public RISCVTargetStreamer {
void emitDirectiveOptionNoPIC() override;
void emitDirectiveOptionRVC() override;
void emitDirectiveOptionNoRVC() override;
- void emitDirectiveOptionAutoCompress() override;
- void emitDirectiveOptionNoAutoCompress() override;
+ void emitDirectiveOptionExact() override;
+ void emitDirectiveOptionNoExact() override;
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args) override;
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index c7091fe246b68..225b9fb88cdaf 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -255,7 +255,7 @@ bool RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst,
const MCSubtargetInfo &SubtargetInfo) {
MCInst CInst;
bool Res = false;
- if (!SubtargetInfo.hasFeature(RISCV::FeatureDisableAsmCompression))
+ if (!SubtargetInfo.hasFeature(RISCV::FeatureExactAssembly))
Res = RISCVRVC::compress(CInst, Inst, SubtargetInfo);
if (Res)
++RISCVNumInstrsCompressed;
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index a0f4c241a6a80..57029b971193a 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1470,9 +1470,9 @@ def FeatureRelax
: SubtargetFeature<"relax", "EnableLinkerRelax", "true",
"Enable Linker relaxation.">;
-def FeatureDisableAsmCompression
- : SubtargetFeature<"disable-asm-compression", "EnableAsmCompression", "false",
- "Disable Automatic Assembly Compression.">;
+def FeatureExactAssembly
+ : SubtargetFeature<"exact-asm", "EnableExactAssembly", "true",
+ "Enable Exact Assembly (Disables Compression and Relaxation)">;
foreach i = {1-31} in
def FeatureReserveX#i :
diff --git a/llvm/test/MC/RISCV/option-autocompress.s b/llvm/test/MC/RISCV/option-exact-compression.s
similarity index 82%
rename from llvm/test/MC/RISCV/option-autocompress.s
rename to llvm/test/MC/RISCV/option-exact-compression.s
index d394f69af0b8a..ae38bf6647d17 100644
--- a/llvm/test/MC/RISCV/option-autocompress.s
+++ b/llvm/test/MC/RISCV/option-exact-compression.s
@@ -21,11 +21,13 @@
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
-# `.option (no)autocompress` enables and disables instruction compression in the
-# assembler, without changing the current architecture.
-#
-# The default is as if `.option autocompress` has been specified, that is, the
-# assembler compresses by default.
+## `.option exact` disables a variety of assembler behaviour:
+## - automatic compression
+## - branch relaxation (of short branches to longer equivalent sequences)
+## - linker relaxation (emitting R_RISCV_RELAX)
+## `.option noexact` enables these behaviours again. It is also the default.
+
+## This test only checks the automatic compression part of this behaviour.
# CHECK-BYTES: 4108
# CHECK-INST: c.lw a0, 0(a0)
@@ -39,8 +41,8 @@ lw a0, 0(a0)
# CHECK: # encoding: [0x08,0x41]
c.lw a0, 0(a0)
-# CHECK: .option noautocompress
-.option noautocompress
+# CHECK: .option exact
+.option exact
# CHECK-BYTES: 00052503
# CHECK-INST: lw a0, 0(a0)
@@ -54,8 +56,8 @@ lw a0, 0(a0)
# CHECK: # encoding: [0x08,0x41]
c.lw a0, 0(a0)
-# CHECK: .option autocompress
-.option autocompress
+# CHECK: .option noexact
+.option noexact
# CHECK-BYTES: 4108
# CHECK-INST: c.lw a0, 0(a0)
diff --git a/llvm/test/MC/RISCV/option-exact-relaxation.s b/llvm/test/MC/RISCV/option-exact-relaxation.s
new file mode 100644
index 0000000000000..ed0a18290c67d
--- /dev/null
+++ b/llvm/test/MC/RISCV/option-exact-relaxation.s
@@ -0,0 +1,74 @@
+# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+relax %s \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+relax %s \
+# RUN: | llvm-objdump --triple=riscv32 --no-show-raw-insn -dr - \
+# RUN: | FileCheck -check-prefixes=CHECK-OBJDUMP %s
+
+# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+relax %s \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+relax %s \
+# RUN: | llvm-objdump --triple=riscv64 --no-show-raw-insn -dr - \
+# RUN: | FileCheck -check-prefixes=CHECK-OBJDUMP %s
+
+## `.option exact` disables a variety of assembler behaviour:
+## - automatic compression
+## - branch relaxation (of short branches to longer equivalent sequences)
+## - linker relaxation (emitting R_RISCV_RELAX)
+## `.option noexact` enables these behaviours again. It is also the default.
+
+## This test only checks the branch and linker relaxation part of this behaviour.
+
+
+
+# CHECK-ASM: call undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_call_plt
+# CHECK-ASM-NEXT: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
+# CHECK-OBJDUMP: auipc ra, 0x0
+# CHECK-OBJDUMP-NEXT: R_RISCV_CALL_PLT undefined
+# CHECK-OBJDUMP-NEXT: R_RISCV_RELAX *ABS*
+# CHECK-OBJDUMP-NEXT: jalr ra
+call undefined at plt
+
+# CHECK-ASM: beq a0, a1, undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
+# CHECK-OBJDUMP: bne a0, a1, 0x10
+# CHECK-OBJDUMP-NEXT: j 0xc
+# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
+beq a0, a1, undefined
+
+# CHECK-ASM: .option exact
+.option exact
+
+# CHECK-ASM: call undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_call_plt
+# CHECK-ASM-NOT: fixup_riscv_relax
+# CHECK-OBJDUMP: auipc ra, 0x0
+# CHECK-OBJDUMP-NEXT: R_RISCV_CALL_PLT undefined
+# CHECK-OBJDUMP-NOT: R_RISCV_RELAX
+# CHECK-OBJDUMP-NEXT: jalr ra
+call undefined at plt
+
+# CHECK-ASM: beq a0, a1, undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
+# CHECK-OBJDUMP: beq a0, a1, 0x18
+# CHECK-OBJDUMP-NEXT: R_RISCV_BRANCH undefined
+beq a0, a1, undefined
+
+# CHECK-ASM: .option noexact
+.option noexact
+
+# CHECK-ASM: call undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_call_plt
+# CHECK-ASM-NEXT: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
+# CHECK-OBJDUMP: auipc ra, 0x0
+# CHECK-OBJDUMP-NEXT: R_RISCV_CALL_PLT undefined
+# CHECK-OBJDUMP-NEXT: R_RISCV_RELAX *ABS*
+# CHECK-OBJDUMP-NEXT: jalr ra
+call undefined at plt
+
+# CHECK-ASM: beq a0, a1, undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
+# CHECK-OBJDUMP: bne a0, a1, 0x2c
+# CHECK-OBJDUMP-NEXT: j 0x28
+# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
+beq a0, a1, undefined
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