[llvm] [AArch64][SVE] Fold integer lane extract and store to FPR store (PR #129756)

[Benjamin Maxwell via llvm-commits]

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@@ -23946,17 +23960,49 @@ static SDValue performSTORECombine(SDNode *N,
   if (SDValue Store = combineBoolVectorAndTruncateStore(DAG, ST))
     return Store;
 
-  if (ST->isTruncatingStore()) {
-    EVT StoreVT = ST->getMemoryVT();
-    if (!isHalvingTruncateOfLegalScalableType(ValueVT, StoreVT))
-      return SDValue();
+  if (ST->isTruncatingStore() &&
+      isHalvingTruncateOfLegalScalableType(ValueVT, MemVT)) {
     if (SDValue Rshrnb =
             trySimplifySrlAddToRshrnb(ST->getOperand(1), DAG, Subtarget)) {
       return DAG.getTruncStore(ST->getChain(), ST, Rshrnb, ST->getBasePtr(),
-                               StoreVT, ST->getMemOperand());
+                               MemVT, ST->getMemOperand());
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MacDue wrote:

It's not entirely unrelated -- previously this was return for any truncating store that's did not match `isHalvingTruncateOfLegalScalableType` (so the pattern I added would not be reachable). 

https://github.com/llvm/llvm-project/pull/129756