[llvm] [llvm] Construct SmallVector with ArrayRef (NFC) (PR #132560)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 22 12:03:32 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Kazu Hirata (kazutakahirata)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/132560.diff
3 Files Affected:
- (modified) llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (+1-1)
- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+1-2)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+1-2)
``````````diff
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 208fa8475fd4f..a9f80860124fb 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -183,7 +183,7 @@ void LegalizerHelper::insertParts(Register DstReg,
// Merge sub-vectors with different number of elements and insert into DstReg.
if (ResultTy.isVector()) {
assert(LeftoverRegs.size() == 1 && "Expected one leftover register");
- SmallVector<Register, 8> AllRegs(PartRegs.begin(), PartRegs.end());
+ SmallVector<Register, 8> AllRegs(PartRegs);
AllRegs.append(LeftoverRegs.begin(), LeftoverRegs.end());
return mergeMixedSubvectors(DstReg, AllRegs);
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 0db6c614684d7..3a45802b24cc1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -17651,8 +17651,7 @@ bool AArch64TargetLowering::lowerInterleaveIntrinsicToStore(
Builder.CreateVectorSplat(StTy->getElementCount(), Builder.getTrue());
auto ExtractedValues = InterleavedValues;
- SmallVector<Value *, 4> StoreOperands(InterleavedValues.begin(),
- InterleavedValues.end());
+ SmallVector<Value *, 4> StoreOperands(InterleavedValues);
if (UseScalable)
StoreOperands.push_back(Pred);
StoreOperands.push_back(BaseAddr);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 78ea3ea3738ae..95476a004cc91 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -23255,8 +23255,7 @@ bool RISCVTargetLowering::lowerInterleaveIntrinsicToStore(
SI->getModule(), FixedVssegIntrIds[Factor - 2],
{InVTy, SI->getPointerOperandType(), XLenTy});
- SmallVector<Value *, 10> Ops(InterleaveValues.begin(),
- InterleaveValues.end());
+ SmallVector<Value *, 10> Ops(InterleaveValues);
Value *VL = ConstantInt::get(XLenTy, FVTy->getNumElements());
Ops.append({SI->getPointerOperand(), VL});
``````````
</details>
https://github.com/llvm/llvm-project/pull/132560
More information about the llvm-commits
mailing list