[llvm] [AMDGPU][True16][CodeGen] fix moveToVALU with proper subreg access in true16 (PR #131859)

[Brox Chen via llvm-commits]

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@@ -6297,6 +6297,12 @@ void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,
       continue;
     }
 
+    // True16 Operands cannot contain VGPR_32 (typically occurs during
+    // SIFixSGPRCopies). True16 instructions are always selected as VOP3
+    if (ST.useRealTrue16Insts() && AMDGPU::isTrue16Inst(Opc) && MO.isReg() &&
+        MRI.getRegClass(MO.getReg()) == &AMDGPU::VGPR_32RegClass)
+      legalizeOpWithMove(MI, Idx);
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broxigarchen wrote:

Proposed another fix here https://github.com/llvm/llvm-project/pull/132089

https://github.com/llvm/llvm-project/pull/131859