[llvm] [MCA] Extend -instruction-tables option with verbosity levels (PR #130574)

[Julien Villette via llvm-commits]

================
@@ -141,6 +241,33 @@ void InstructionInfoView::collectData(
     IIVDEntry.mayLoad = MCDesc.mayLoad();
     IIVDEntry.mayStore = MCDesc.mayStore();
     IIVDEntry.hasUnmodeledSideEffects = MCDesc.hasUnmodeledSideEffects();
+
+    if (PrintFullInfo) {
+      // Get latency with bypass
+      IIVDEntry.Bypass =
+          IIVDEntry.Latency - MCSchedModel::getBypassDelayCycles(STI, SCDesc);
+      IIVDEntry.OpcodeName = MCII.getName(Inst.getOpcode());
+      raw_string_ostream TempStream(IIVDEntry.Resources);
+      const MCWriteProcResEntry *Index = STI.getWriteProcResBegin(&SCDesc);
+      const MCWriteProcResEntry *Last = STI.getWriteProcResEnd(&SCDesc);
+      auto Sep = "";
+      for (; Index != Last; ++Index) {
+        if (!Index->ReleaseAtCycle)
+          continue;
+        const MCProcResourceDesc *MCProc =
+            SM.getProcResource(Index->ProcResourceIdx);
+        if (Index->ReleaseAtCycle > 1) {
----------------
jvillette38 wrote:

Resource format modified:
```
if ReleaseAtCycle == 1 then <Resource Name>
if ReleaseAtCycle > 1 and AcquireAtCycle == 0 then <Resource Name>[<ReleaseAtCycle>]
if ReleaseAtCycle > 1 and AcquireAtCycle > 0 then <Resource Name>[<AcquireAtCycle>,<ReleaseAtCycle>]
```
Example with these RISCV instructions:
```
vsetvli a3, a2, e16, m1, tu, mu`
vlm.v   v4, (a1)`
```
`llvm-mca  -mtriple=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=full ./test.s`
Output:

```
Resources:
[0]   - SiFive7FDiv:1
[1]   - SiFive7IDiv:1
[2]   - SiFive7PipeA:1
[3]   - SiFive7PipeAB:2 SiFive7PipeA, SiFive7PipeB
[4]   - SiFive7PipeB:1
[5]   - SiFive7VA:1
[6]   - SiFive7VCQ:1
[7]   - SiFive7VL:1
[8]   - SiFive7VS:1


Instruction Info:
[1]: #uOps
[2]: Latency
[3]: RThroughput
[4]: MayLoad
[5]: MayStore
[6]: HasSideEffects (U)
[7]: Bypass Latency
[8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
[9]: LLVM Opcode Name

[1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]                                                      [9]                        Instructions:
 1      3     1.00                  U      1      SiFive7PipeA,SiFive7PipeAB                               VSETVLI                   vsetvli    a3, a2, e16, m1, tu, mu
 1      4     3.00    *                    4      SiFive7VCQ,SiFive7VL[1,3]                                VLM_V                     vlm.v      v4, (a1)
```


https://github.com/llvm/llvm-project/pull/130574