[llvm] ff9c5c3 - [shrinkwrap] PowerPC's FP register should be honored when processing the save point for prologue. (#129855)
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Fri Mar 21 09:55:42 PDT 2025
Author: Tony Varghese
Date: 2025-03-21T12:55:39-04:00
New Revision: ff9c5c334ad4a93b33703396a401838df2dedc35
URL: https://github.com/llvm/llvm-project/commit/ff9c5c334ad4a93b33703396a401838df2dedc35
DIFF: https://github.com/llvm/llvm-project/commit/ff9c5c334ad4a93b33703396a401838df2dedc35.diff
LOG: [shrinkwrap] PowerPC's FP register should be honored when processing the save point for prologue. (#129855)
When generating code for functions that have `__builtin_frame_address`
calls and `noinline` attribute, prologue was not emitted correctly
leading to an assertion failure in PowerPC. The issue was due to
improper insertion of prologue for a function that contain llvm
`__builtin_frame_address`.
Shrink-wrap pass computes the save and restore points of a function.
Default points are the entry and exit points of the function. During
shrink-wrapping the frame-pointer was not honored like the stack pointer
and it was considered as a callee-saved register. This change will treat
the FP similar to SP and will insert the prolog on top the instruction
containing FP.
---------
Co-authored-by: Tony Varghese <tony.varghese at ibm.com>
Added:
Modified:
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/lib/CodeGen/ShrinkWrap.cpp
llvm/lib/Target/PowerPC/PPCRegisterInfo.h
llvm/test/CodeGen/PowerPC/shrink-wrap-frame-pointer.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index e4fad8f9ec869..6180c53a9a949 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -1246,6 +1246,11 @@ class TargetRegisterInfo : public MCRegisterInfo {
return false;
}
+ /// Some targets delay assigning the frame until late and use a placeholder
+ /// to represent it earlier. This method can be used to identify the frame
+ /// register placeholder.
+ virtual bool isVirtualFrameRegister(MCRegister Reg) const { return false; }
+
virtual std::optional<uint8_t> getVRegFlagValue(StringRef Name) const {
return {};
}
diff --git a/llvm/lib/CodeGen/ShrinkWrap.cpp b/llvm/lib/CodeGen/ShrinkWrap.cpp
index fa57eb30fac43..9d81d28bcaf1c 100644
--- a/llvm/lib/CodeGen/ShrinkWrap.cpp
+++ b/llvm/lib/CodeGen/ShrinkWrap.cpp
@@ -348,10 +348,14 @@ bool ShrinkWrap::useOrDefCSROrFI(const MachineInstr &MI, RegScavenger *RS,
// calling convention definitions, so we need to watch for it, too. An LR
// mentioned implicitly by a return (or "branch to link register")
// instruction we can ignore, otherwise we may pessimize shrinkwrapping.
- UseOrDefCSR =
- (!MI.isCall() && PhysReg == SP) ||
- RCI.getLastCalleeSavedAlias(PhysReg) ||
- (!MI.isReturn() && TRI->isNonallocatableRegisterCalleeSave(PhysReg));
+ // PPC's Frame pointer (FP) is also not described as a callee-saved
+ // register. Until the FP is assigned a Physical Register PPC's FP needs
+ // to be checked separately.
+ UseOrDefCSR = (!MI.isCall() && PhysReg == SP) ||
+ RCI.getLastCalleeSavedAlias(PhysReg) ||
+ (!MI.isReturn() &&
+ TRI->isNonallocatableRegisterCalleeSave(PhysReg)) ||
+ TRI->isVirtualFrameRegister(PhysReg);
} else if (MO.isRegMask()) {
// Check if this regmask clobbers any of the CSRs.
for (unsigned Reg : getCurrentCSRs(RS)) {
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
index 274c7cb68ae0a..103059d0e29ab 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -176,6 +176,10 @@ class PPCRegisterInfo : public PPCGenRegisterInfo {
bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const override {
return Reg == PPC::LR || Reg == PPC::LR8;
}
+
+ bool isVirtualFrameRegister(MCRegister Reg) const override {
+ return Reg == PPC::FP || Reg == PPC::FP8;
+ }
};
} // end namespace llvm
diff --git a/llvm/test/CodeGen/PowerPC/shrink-wrap-frame-pointer.ll b/llvm/test/CodeGen/PowerPC/shrink-wrap-frame-pointer.ll
index a06007c6f4c67..1b30a56253b75 100644
--- a/llvm/test/CodeGen/PowerPC/shrink-wrap-frame-pointer.ll
+++ b/llvm/test/CodeGen/PowerPC/shrink-wrap-frame-pointer.ll
@@ -7,24 +7,37 @@
define void @foo(ptr noundef readnone %parent_frame_pointer) {
; POWERPC64-LABEL: foo
; POWERPC64: # %bb.0:
-; POWERPC64-NEXT: cmpld [[REG1:[0-9]+]], 1
-; POWERPC64: # %bb.1:
-; POWERPC64-NEXT: mflr [[REG2:[0-9]+]]
+; POWERPC64: mflr [[REG1:[0-9]+]]
; POWERPC64-NEXT: stdu 1, -32(1)
+; POWERPC64-NEXT: std [[REG1]], 48(1)
+; POWERPC64: cmpld [[REG2:[0-9]+]], 1
+; POWERPC64: # %bb.1:
+; POWERPC64-NEXT: addi 1, 1, 32
+; POWERPC64-NEXT: ld [[REG1]], 16(1)
+; POWERPC64-NEXT: mtlr [[REG1]]
+; POWERPC64-NEXT: blr
; POWERPC32-AIX-LABEL: .foo:
; POWERPC32-AIX: # %bb.0:
-; POWERPC32-AIX-NEXT: cmplw [[REG1:[0-9]+]], 1
-; POWERPC32-AIX: # %bb.1:
-; POWERPC32-AIX-NEXT: mflr [[REG2:[0-9]+]]
+; POWERPC32-AIX-NEXT: mflr [[REG1:[0-9]+]]
; POWERPC32-AIX-NEXT: stwu 1, -64(1)
+; POWERPC32-AIX-NEXT: cmplw [[REG2:[0-9]+]], 1
+; POWERPC32-AIX: # %bb.1:
+; POWERPC32-AIX-NEXT: addi 1, 1, 64
+; POWERPC32-AIX-NEXT: lwz [[REG1]], 8(1)
+; POWERPC32-AIX-NEXT: mtlr [[REG1]]
+; POWERPC32-AIX-NEXT: blr
; POWERPC64-AIX-LABEL: .foo:
; POWERPC64-AIX: # %bb.0:
-; POWERPC64-AIX-NEXT: cmpld [[REG1:[0-9]+]], 1
-; POWERPC64-AIX: # %bb.1:
-; POWERPC64-AIX-NEXT: mflr [[REG2:[0-9]+]]
+; POWERPC64-AIX-NEXT: mflr [[REG1:[0-9]+]]
; POWERPC64-AIX-NEXT: stdu 1, -112(1)
+; POWERPC64-AIX-NEXT: cmpld [[REG2:[0-9]+]], 1
+; POWERPC64-AIX: # %bb.1:
+; POWERPC64-AIX-NEXT: addi 1, 1, 112
+; POWERPC64-AIX-NEXT: ld [[REG1]], 16(1)
+; POWERPC64-AIX-NEXT: mtlr [[REG1]]
+; POWERPC64-AIX-NEXT: blr
entry:
%frameaddress = tail call ptr @llvm.frameaddress.p0(i32 0)
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