[llvm] [RISCV] Correct qc.e.li instruction definition (PR #132380)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Sudharsan Veeravalli (svs-quic)

<details>
<summary>Changes</summary>

The instruction has no tied operands. It was incorrectly using QCIRVInstEAI which has a tied operand for the destination register.

---
Full diff: https://github.com/llvm/llvm-project/pull/132380.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+10-1) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index c009bd3b24682..86d31937ab7a2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -726,7 +726,16 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
     let Inst{15-12} = imm20{18-15};
   }
 
-  def QC_E_LI : QCIRVInstEAI<0b000, 0b0, "qc.e.li">;
+  def QC_E_LI : RVInst48<(outs GPRNoX0:$rd), (ins simm32:$imm),
+                         "qc.e.li", "$rd, $imm", [], InstFormatOther> {
+    bits<5> rd;
+    bits<32> imm;
+
+    let Inst{47-16} = imm;
+    let Inst{15-12} = 0b0000;
+    let Inst{11-7} = rd;
+    let Inst{6-0} = 0b0011111;
+  }
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 } // Predicates = [HasVendorXqcili, IsRV32]
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/132380