[llvm] [RISCV] Set isTrap for EBREAK and UNIMP (PR #131636)

[Alex Bradbury via llvm-commits]

https://github.com/asb updated https://github.com/llvm/llvm-project/pull/131636

>From 7dba3c00a85d1e8abc7dd025081105b95a207898 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb at igalia.com>
Date: Mon, 17 Mar 2025 15:49:50 +0000
Subject: [PATCH 1/2] [RISCV] Set isTrap for EBREAK and UNIMP

This is done for completeness. The property isn't used in upstream
llvm/, although it is queried in BOLT in MCPlusBuilder.cpp.
---
 llvm/lib/Target/RISCV/RISCVInstrInfo.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 11d93892ee7a5..6be4fb1db602d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -752,6 +752,7 @@ def ECALL : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ecall", "">, Sched<[Write
   let imm12 = 0;
 }
 
+let isTrap = 1 in
 def EBREAK : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ebreak", "">,
              Sched<[]> {
   let rs1 = 0;
@@ -762,6 +763,7 @@ def EBREAK : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ebreak", "">,
 // This is a de facto standard (as set by GNU binutils) 32-bit unimplemented
 // instruction (i.e., it should always trap, if your implementation has invalid
 // instruction traps).
+let isTrap = 1 in
 def UNIMP : RVInstI<0b001, OPC_SYSTEM, (outs), (ins), "unimp", "">,
             Sched<[]> {
   let rs1 = 0;

>From d6b3260ee8bd109233832b79db6410b1c9ced0d9 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb at igalia.com>
Date: Tue, 18 Mar 2025 14:59:57 +0000
Subject: [PATCH 2/2] Add isTrap to C_UNIMP

---
 llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index 41ed253f2f36d..727291c48a611 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -596,7 +596,7 @@ def C_SDSP : CStackStore<0b111, "c.sdsp", GPR, uimm9_lsb000>,
 
 // The all zeros pattern isn't a valid RISC-V instruction. It's used by GNU
 // binutils as 16-bit instruction known to be unimplemented (i.e., trapping).
-let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0, isTrap = 1 in
 def C_UNIMP : RVInst16<(outs), (ins), "c.unimp", "", [], InstFormatOther>,
               Sched<[]> {
   let Inst{15-0} = 0;