[llvm] [NVPTX] Improve 64bit FSH/ROT lowering when shift amount is constant (PR #131371)

[Justin Fargnoli via llvm-commits]

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@@ -445,6 +448,17 @@ bool NVPTXDAGToDAGISel::SelectSETP_BF16X2(SDNode *N) {
   return true;
 }
 
+bool NVPTXDAGToDAGISel::tryUNPACK_VECTOR(SDNode *N) {
+  SDValue Vector = N->getOperand(0);
+  MVT EltVT = N->getSimpleValueType(0);
+
+  MachineSDNode *N2 =
+      CurDAG->getMachineNode(NVPTX::I64toV2I32, SDLoc(N), EltVT, EltVT, Vector);
+
+  ReplaceNode(N, N2);
+  return true;
+}
+
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justinfargnoli wrote:

Why can't this be done in `NVPTXInstrInfo.td`?

https://github.com/llvm/llvm-project/pull/131371