[llvm] AMDGPU: Fix broken check prefix and degraded cov4 test coverage (PR #131757)

via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 18 01:47:39 PDT 2025 

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/131757.diff


2 Files Affected:

- (added) llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v4.ll (+101) 
- (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v5.ll (+15-9) 


``````````diff
diff --git a/llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v4.ll b/llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v4.ll
new file mode 100644
index 0000000000000..50bbe1d7af6c6
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v4.ll
@@ -0,0 +1,101 @@
+; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -passes=amdgpu-attributor -o %t.gfx7.bc %s
+; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -passes=amdgpu-attributor -o %t.gfx8.bc %s
+; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=amdgpu-attributor -o %t.gfx9.bc %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %t.gfx7.bc | FileCheck --check-prefixes=CHECK,PRE-GFX9 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %t.gfx8.bc | FileCheck --check-prefixes=CHECK,PRE-GFX9 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %t.gfx9.bc | FileCheck --check-prefixes=CHECK,GFX9 %s
+
+; CHECK: addrspacecast_requires_queue_ptr
+; PRE-GFX9: .amdhsa_user_sgpr_queue_ptr 1
+; GFX9: .amdhsa_user_sgpr_queue_ptr 0
+
+; CHECK: is_shared_requires_queue_ptr
+; PRE-GFX9: .amdhsa_user_sgpr_queue_ptr 1
+; GFX9: .amdhsa_user_sgpr_queue_ptr 0
+
+; CHECK: is_private_requires_queue_ptr
+; PRE-GFX9: .amdhsa_user_sgpr_queue_ptr 1
+; GFX9: .amdhsa_user_sgpr_queue_ptr 0
+
+; CHECK: trap_requires_queue_ptr
+; PRE-GFX9: .amdhsa_user_sgpr_queue_ptr 1
+; GFX9: .amdhsa_user_sgpr_queue_ptr 0
+
+; CHECK: amdgcn_queue_ptr_requires_queue_ptr
+; CHECK: .amdhsa_user_sgpr_queue_ptr 1
+
+
+; On gfx8, the queue ptr is required for this addrspacecast.
+; CHECK: - .args:
+; CHECK-NOT:		hidden_queue_ptr
+; CHECK-LABEL:		.name:           addrspacecast_requires_queue_ptr
+define amdgpu_kernel void @addrspacecast_requires_queue_ptr(ptr addrspace(5) %ptr.private, ptr addrspace(3) %ptr.local) {
+  %flat.private = addrspacecast ptr addrspace(5) %ptr.private to ptr
+  %flat.local = addrspacecast ptr addrspace(3) %ptr.local to ptr
+  store volatile i32 1, ptr %flat.private
+  store volatile i32 2, ptr %flat.local
+  ret void
+}
+
+
+; CHECK: - .args:
+; CHECK-NOT:		hidden_shared_base
+; CHECK-LABEL:		.name:          is_shared_requires_queue_ptr
+define amdgpu_kernel void @is_shared_requires_queue_ptr(ptr %ptr) {
+  %is.shared = call i1 @llvm.amdgcn.is.shared(ptr %ptr)
+  %zext = zext i1 %is.shared to i32
+  store volatile i32 %zext, ptr addrspace(1) poison
+  ret void
+}
+
+; CHECK: - .args:
+; CHECK-NOT: hidden_shared_base
+; CHECK-NOT: hidden_private_base
+; CHECK-NOT: hidden_queue_ptr
+; CHECK-LABEL:		.name:           is_private_requires_queue_ptr
+define amdgpu_kernel void @is_private_requires_queue_ptr(ptr %ptr) {
+  %is.private = call i1 @llvm.amdgcn.is.private(ptr %ptr)
+  %zext = zext i1 %is.private to i32
+  store volatile i32 %zext, ptr addrspace(1) poison
+  ret void
+}
+
+; CHECK: - .args:
+
+; CHECK-NOT: hidden_shared_base
+; CHECK-NOT: hidden_private_base
+; CHECK-NOT: hidden_queue_ptr
+; CHECK-LABEL:		.name:           trap_requires_queue_ptr
+define amdgpu_kernel void @trap_requires_queue_ptr() {
+  call void @llvm.trap()
+  unreachable
+}
+
+; CHECK: - .args:
+; CHECK-NOT: hidden_queue_ptr
+; CHECK-NOT: hidden_shared_base
+; CHECK-NOT: hidden_private_base
+; CHECK-LABEL:		.name:           amdgcn_queue_ptr_requires_queue_ptr
+define amdgpu_kernel void @amdgcn_queue_ptr_requires_queue_ptr(ptr addrspace(1) %ptr)  {
+  %queue.ptr = call ptr addrspace(4) @llvm.amdgcn.queue.ptr()
+  %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+  %dispatch.ptr = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
+  %dispatch.id = call i64 @llvm.amdgcn.dispatch.id()
+  %queue.load = load volatile i8, ptr addrspace(4) %queue.ptr
+  %implicitarg.load = load volatile i8, ptr addrspace(4) %implicitarg.ptr
+  %dispatch.load = load volatile i8, ptr addrspace(4) %dispatch.ptr
+  store volatile i64 %dispatch.id, ptr addrspace(1) %ptr
+  ret void
+}
+
+declare noalias ptr addrspace(4) @llvm.amdgcn.queue.ptr()
+declare noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+declare i64 @llvm.amdgcn.dispatch.id()
+declare noalias ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
+declare i1 @llvm.amdgcn.is.shared(ptr)
+declare i1 @llvm.amdgcn.is.private(ptr)
+declare void @llvm.trap()
+declare void @llvm.debugtrap()
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
diff --git a/llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v5.ll b/llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v5.ll
index 5a7986e15ead9..84d6480478d0a 100644
--- a/llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v5.ll
+++ b/llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v5.ll
@@ -1,18 +1,24 @@
 ; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -passes=amdgpu-attributor -o %t.gfx7.bc %s
 ; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -passes=amdgpu-attributor -o %t.gfx8.bc %s
 ; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=amdgpu-attributor -o %t.gfx9.bc %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj < %t.gfx7.bc | llvm-readelf --notes - | FileCheck --check-prefix=CHECK  %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -filetype=obj < %t.gfx8.bc | llvm-readelf --notes - | FileCheck --check-prefix=CHECK  %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj < %t.gfx9.bc | llvm-readelf --notes - | FileCheck --check-prefixes=CHECK,GFX9  %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %t.gfx7.bc | FileCheck --check-prefix=CHECK %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %t.gfx8.bc | FileCheck --check-prefix=CHECK %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %t.gfx9.bc | FileCheck --check-prefixes=CHECK,GFX9 %s
+; xUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj < %t.gfx7.bc | llvm-readelf --notes - | FileCheck --check-prefixes=CHECK,PRE-GFX9  %s
+; xUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -filetype=obj < %t.gfx8.bc | llvm-readelf --notes - | FileCheck --check-prefixes=CHECK,PRE-GFX9  %s
+; xUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj < %t.gfx9.bc | llvm-readelf --notes - | FileCheck --check-prefixes=CHECK,GFX9  %s
+; xUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %t.gfx7.bc | FileCheck --check-prefixes=CHECK,PRE-GFX9 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %t.gfx8.bc | FileCheck --check-prefixes=CHECK,PRE-GFX9 %s
+; xUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %t.gfx9.bc | FileCheck --check-prefixes=CHECK,GFX9 %s
 
 
-; On gfx8, the queue ptr is required for this addrspacecast.
+; On gfx8, the queue ptr is required for this addrspacecast on cov4
 ; CHECK: - .args:
-; PRE-GFX9:		hidden_queue_ptr
-; GFX9-NOT:		hidden_queue_ptr
+
+; PRE-GFX9: .value_kind:     hidden_private_base
+; PRE-GFX9: .value_kind:     hidden_shared_base
+
+; GFX9-NOT: hidden_queue_ptr
+; GFX9-NOT: hidden_private_base
+; GFX9-NOT: hidden_shared_base
+
 ; CHECK-LABEL:		.name:           addrspacecast_requires_queue_ptr
 define amdgpu_kernel void @addrspacecast_requires_queue_ptr(ptr addrspace(5) %ptr.private, ptr addrspace(3) %ptr.local) {
   %flat.private = addrspacecast ptr addrspace(5) %ptr.private to ptr

``````````

</details>


https://github.com/llvm/llvm-project/pull/131757

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