[llvm] [AArch64][SVE] Add dot product lowering for PARTIAL_REDUCE_MLA node (PR #130933)

[Benjamin Maxwell via llvm-commits]

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@@ -3658,6 +3687,12 @@ class TargetLoweringBase {
   /// up the MVT::VALUETYPE_SIZE value to the next multiple of 8.
   uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::VALUETYPE_SIZE + 7) / 8];
 
+  /// For each result type and input type for the ISD::PARTIAL_REDUCE_U/SMLA
+  /// nodes, keep a LegalizeAction which indicates how instruction selection
+  /// should deal with this operation.
+  LegalizeAction PartialReduceMLAActions[MVT::VALUETYPE_SIZE]
+                                        [MVT::VALUETYPE_SIZE];
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MacDue wrote:

`MVT::VALUETYPE_SIZE` currently is 237, so this table is 237*237 = 56,169 entries, almost all empty. 

I think a `DenseMap` or `SmallVector` would be fine here. Alternatively, we could just skip the table and inline the logic into `getPartialReduceMLAAction()` -- it seems pretty simple. 

https://github.com/llvm/llvm-project/pull/130933