[llvm] [RISCV] Support .option {no}exact (PR #122483)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 19 13:58:02 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Sam Elliott (lenary)
<details>
<summary>Changes</summary>
This implements [the `.option exact` and `.option noexact` proposal](https://github.com/riscv-non-isa/riscv-asm-manual/pull/122) for RISC-V.
`.option exact` turns off:
- Compression
- Branch Relaxation
- Linker Relaxation
`.option noexact` turns these back on, and is also the default, matching the current behaviour.
---
Full diff: https://github.com/llvm/llvm-project/pull/122483.diff
10 Files Affected:
- (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+29-5)
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp (+10)
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp (+2)
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h (+2)
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp (+10)
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h (+4)
- (modified) llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp (+3-1)
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+4)
- (added) llvm/test/MC/RISCV/option-exact-compression.s (+72)
- (added) llvm/test/MC/RISCV/option-exact-relaxation.s (+74)
``````````diff
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index ce25380cbdda2..8dd428a1ba461 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3173,6 +3173,26 @@ bool RISCVAsmParser::parseDirectiveOption() {
return false;
}
+ if (Option == "exact") {
+ if (Parser.parseEOL())
+ return true;
+
+ getTargetStreamer().emitDirectiveOptionExact();
+ setFeatureBits(RISCV::FeatureExactAssembly, "exact-asm");
+ clearFeatureBits(RISCV::FeatureRelax, "relax");
+ return false;
+ }
+
+ if (Option == "noexact") {
+ if (Parser.parseEOL())
+ return true;
+
+ getTargetStreamer().emitDirectiveOptionNoExact();
+ clearFeatureBits(RISCV::FeatureExactAssembly, "exact-asm");
+ setFeatureBits(RISCV::FeatureRelax, "relax");
+ return false;
+ }
+
if (Option == "rvc") {
if (Parser.parseEOL())
return true;
@@ -3229,9 +3249,10 @@ bool RISCVAsmParser::parseDirectiveOption() {
}
// Unknown option.
- Warning(Parser.getTok().getLoc(), "unknown option, expected 'push', 'pop', "
- "'rvc', 'norvc', 'arch', 'relax' or "
- "'norelax'");
+ Warning(Parser.getTok().getLoc(),
+ "unknown option, expected 'push', 'pop', "
+ "'rvc', 'norvc', 'arch', 'relax', 'norelax', "
+ "'exact' or 'noexact'");
Parser.eatToEndOfStatement();
return false;
}
@@ -3441,10 +3462,13 @@ bool RISCVAsmParser::parseDirectiveVariantCC() {
void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
MCInst CInst;
- bool Res = RISCVRVC::compress(CInst, Inst, getSTI());
+ bool Res = false;
+ const MCSubtargetInfo &STI = getSTI();
+ if (!STI.hasFeature(RISCV::FeatureExactAssembly))
+ Res = RISCVRVC::compress(CInst, Inst, STI);
if (Res)
++RISCVNumInstrsCompressed;
- S.emitInstruction((Res ? CInst : Inst), getSTI());
+ S.emitInstruction((Res ? CInst : Inst), STI);
}
void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index e752b0ec5f58c..83e6f7169e957 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -344,6 +344,10 @@ std::pair<bool, bool> RISCVAsmBackend::relaxLEB128(const MCAssembler &Asm,
// Given a compressed control flow instruction this function returns
// the expanded instruction.
unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
+ // Disable relaxation if FeatureExactAssembly
+ if (STI.hasFeature(RISCV::FeatureExactAssembly))
+ return Op;
+
switch (Op) {
default:
return Op;
@@ -371,6 +375,12 @@ unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,
const MCSubtargetInfo &STI) const {
+ // This function has access to two STIs, the member of the AsmBackend, and the
+ // one passed as an argument. The latter is more specific, so we query it for
+ // specific features.
+ if (STI.hasFeature(RISCV::FeatureExactAssembly))
+ return false;
+
return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index 9eabc61331832..1814ca2a077f3 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -53,6 +53,8 @@ void RISCVTargetELFStreamer::emitDirectiveOptionPIC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoPIC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionRVC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoRVC() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionExact() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionNoExact() {}
void RISCVTargetELFStreamer::emitDirectiveOptionRelax() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoRelax() {}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
index e1765805b4a26..bf84f8e700e6d 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
@@ -62,6 +62,8 @@ class RISCVTargetELFStreamer : public RISCVTargetStreamer {
void emitDirectiveOptionNoPIC() override;
void emitDirectiveOptionRVC() override;
void emitDirectiveOptionNoRVC() override;
+ void emitDirectiveOptionExact() override;
+ void emitDirectiveOptionNoExact() override;
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
void emitDirectiveVariantCC(MCSymbol &Symbol) override;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index ce64c61034901..04a0feb98eec2 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -39,6 +39,8 @@ void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
+void RISCVTargetStreamer::emitDirectiveOptionExact() {}
+void RISCVTargetStreamer::emitDirectiveOptionNoExact() {}
void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
void RISCVTargetStreamer::emitDirectiveOptionArch(
@@ -125,6 +127,14 @@ void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {
OS << "\t.option\tnorvc\n";
}
+void RISCVTargetAsmStreamer::emitDirectiveOptionExact() {
+ OS << "\t.option\texact\n";
+}
+
+void RISCVTargetAsmStreamer::emitDirectiveOptionNoExact() {
+ OS << "\t.option\tnoexact\n";
+}
+
void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
OS << "\t.option\trelax\n";
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
index cb8bc21cb6355..a23ac19c0cabb 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
@@ -47,6 +47,8 @@ class RISCVTargetStreamer : public MCTargetStreamer {
virtual void emitDirectiveOptionNoPIC();
virtual void emitDirectiveOptionRVC();
virtual void emitDirectiveOptionNoRVC();
+ virtual void emitDirectiveOptionExact();
+ virtual void emitDirectiveOptionNoExact();
virtual void emitDirectiveOptionRelax();
virtual void emitDirectiveOptionNoRelax();
virtual void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args);
@@ -84,6 +86,8 @@ class RISCVTargetAsmStreamer : public RISCVTargetStreamer {
void emitDirectiveOptionNoPIC() override;
void emitDirectiveOptionRVC() override;
void emitDirectiveOptionNoRVC() override;
+ void emitDirectiveOptionExact() override;
+ void emitDirectiveOptionNoExact() override;
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args) override;
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 12519c86bf44b..225b9fb88cdaf 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -254,7 +254,9 @@ void RISCVAsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
bool RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst,
const MCSubtargetInfo &SubtargetInfo) {
MCInst CInst;
- bool Res = RISCVRVC::compress(CInst, Inst, SubtargetInfo);
+ bool Res = false;
+ if (!SubtargetInfo.hasFeature(RISCV::FeatureExactAssembly))
+ Res = RISCVRVC::compress(CInst, Inst, SubtargetInfo);
if (Res)
++RISCVNumInstrsCompressed;
S.emitInstruction(Res ? CInst : Inst, SubtargetInfo);
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index f23a855e7049f..57029b971193a 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1470,6 +1470,10 @@ def FeatureRelax
: SubtargetFeature<"relax", "EnableLinkerRelax", "true",
"Enable Linker relaxation.">;
+def FeatureExactAssembly
+ : SubtargetFeature<"exact-asm", "EnableExactAssembly", "true",
+ "Enable Exact Assembly (Disables Compression and Relaxation)">;
+
foreach i = {1-31} in
def FeatureReserveX#i :
SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
diff --git a/llvm/test/MC/RISCV/option-exact-compression.s b/llvm/test/MC/RISCV/option-exact-compression.s
new file mode 100644
index 0000000000000..ae38bf6647d17
--- /dev/null
+++ b/llvm/test/MC/RISCV/option-exact-compression.s
@@ -0,0 +1,72 @@
+# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c %s \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c \
+# RUN: -M no-aliases %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c %s \
+# RUN: | llvm-objdump --triple=riscv32 --mattr=+c --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c %s \
+# RUN: | llvm-objdump --triple=riscv32 --mattr=+c --no-print-imm-hex -d -M no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
+
+# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c %s \
+# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c \
+# RUN: -M no-aliases %s | FileCheck -check-prefixes=CHECK-INST %s
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c %s \
+# RUN: | llvm-objdump --triple=riscv64 --mattr=+c --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c %s \
+# RUN: | llvm-objdump --triple=riscv64 --mattr=+c --no-print-imm-hex -d -M no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
+
+
+## `.option exact` disables a variety of assembler behaviour:
+## - automatic compression
+## - branch relaxation (of short branches to longer equivalent sequences)
+## - linker relaxation (emitting R_RISCV_RELAX)
+## `.option noexact` enables these behaviours again. It is also the default.
+
+## This test only checks the automatic compression part of this behaviour.
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+lw a0, 0(a0)
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+c.lw a0, 0(a0)
+
+# CHECK: .option exact
+.option exact
+
+# CHECK-BYTES: 00052503
+# CHECK-INST: lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x03,0x25,0x05,0x00]
+lw a0, 0(a0)
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+c.lw a0, 0(a0)
+
+# CHECK: .option noexact
+.option noexact
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+lw a0, 0(a0)
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+c.lw a0, 0(a0)
diff --git a/llvm/test/MC/RISCV/option-exact-relaxation.s b/llvm/test/MC/RISCV/option-exact-relaxation.s
new file mode 100644
index 0000000000000..ed0a18290c67d
--- /dev/null
+++ b/llvm/test/MC/RISCV/option-exact-relaxation.s
@@ -0,0 +1,74 @@
+# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+relax %s \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+relax %s \
+# RUN: | llvm-objdump --triple=riscv32 --no-show-raw-insn -dr - \
+# RUN: | FileCheck -check-prefixes=CHECK-OBJDUMP %s
+
+# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+relax %s \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+relax %s \
+# RUN: | llvm-objdump --triple=riscv64 --no-show-raw-insn -dr - \
+# RUN: | FileCheck -check-prefixes=CHECK-OBJDUMP %s
+
+## `.option exact` disables a variety of assembler behaviour:
+## - automatic compression
+## - branch relaxation (of short branches to longer equivalent sequences)
+## - linker relaxation (emitting R_RISCV_RELAX)
+## `.option noexact` enables these behaviours again. It is also the default.
+
+## This test only checks the branch and linker relaxation part of this behaviour.
+
+
+
+# CHECK-ASM: call undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_call_plt
+# CHECK-ASM-NEXT: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
+# CHECK-OBJDUMP: auipc ra, 0x0
+# CHECK-OBJDUMP-NEXT: R_RISCV_CALL_PLT undefined
+# CHECK-OBJDUMP-NEXT: R_RISCV_RELAX *ABS*
+# CHECK-OBJDUMP-NEXT: jalr ra
+call undefined at plt
+
+# CHECK-ASM: beq a0, a1, undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
+# CHECK-OBJDUMP: bne a0, a1, 0x10
+# CHECK-OBJDUMP-NEXT: j 0xc
+# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
+beq a0, a1, undefined
+
+# CHECK-ASM: .option exact
+.option exact
+
+# CHECK-ASM: call undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_call_plt
+# CHECK-ASM-NOT: fixup_riscv_relax
+# CHECK-OBJDUMP: auipc ra, 0x0
+# CHECK-OBJDUMP-NEXT: R_RISCV_CALL_PLT undefined
+# CHECK-OBJDUMP-NOT: R_RISCV_RELAX
+# CHECK-OBJDUMP-NEXT: jalr ra
+call undefined at plt
+
+# CHECK-ASM: beq a0, a1, undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
+# CHECK-OBJDUMP: beq a0, a1, 0x18
+# CHECK-OBJDUMP-NEXT: R_RISCV_BRANCH undefined
+beq a0, a1, undefined
+
+# CHECK-ASM: .option noexact
+.option noexact
+
+# CHECK-ASM: call undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_call_plt
+# CHECK-ASM-NEXT: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
+# CHECK-OBJDUMP: auipc ra, 0x0
+# CHECK-OBJDUMP-NEXT: R_RISCV_CALL_PLT undefined
+# CHECK-OBJDUMP-NEXT: R_RISCV_RELAX *ABS*
+# CHECK-OBJDUMP-NEXT: jalr ra
+call undefined at plt
+
+# CHECK-ASM: beq a0, a1, undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
+# CHECK-OBJDUMP: bne a0, a1, 0x2c
+# CHECK-OBJDUMP-NEXT: j 0x28
+# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
+beq a0, a1, undefined
``````````
</details>
https://github.com/llvm/llvm-project/pull/122483
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