[llvm] [RISCV] Update some of the RVV memory ops in SiFive P400 & P600 sched models (PR #129575)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,542 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf2, ta, ma
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topperc wrote:

Can we sort these by increasing lmul size so mf8 is before mf4 is before mf2.

https://github.com/llvm/llvm-project/pull/129575