[llvm] [NFC][AMDGPU] Compute always reserved registers once (PR #132006)

[Akshat Oke via llvm-commits]

https://github.com/optimisan updated https://github.com/llvm/llvm-project/pull/132006

>From cca3f5da1be349d4258e26987e9ba6e9b64edad7 Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Wed, 19 Mar 2025 11:26:09 +0000
Subject: [PATCH 1/2] [NFC][AMDGPU] Compute always reserved registers once

---
 llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 18 +++++++++++++++---
 llvm/lib/Target/AMDGPU/SIRegisterInfo.h   |  3 +++
 2 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index c1ac9491b2363..1ab3dbcc97fc3 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -629,12 +629,17 @@ SIRegisterInfo::getMaxNumVectorRegs(const MachineFunction &MF) const {
   return std::pair(MaxNumVGPRs, MaxNumAGPRs);
 }
 
-BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+BitVector SIRegisterInfo::AlwaysReservedRegs;
+
+BitVector SIRegisterInfo::getAlwaysReservedRegs() const {
+  // Already been calculated, so do not compute again.
+  if (AlwaysReservedRegs.size() == getNumRegs()) {
+    return AlwaysReservedRegs;
+  }
+
   BitVector Reserved(getNumRegs());
   Reserved.set(AMDGPU::MODE);
 
-  const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
-
   // Reserve special purpose registers.
   //
   // EXEC_LO and EXEC_HI could be allocated and used as regular register, but
@@ -680,6 +685,12 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   // Reserve null register - it shall never be allocated
   reserveRegisterTuples(Reserved, AMDGPU::SGPR_NULL64);
 
+  return this->AlwaysReservedRegs = Reserved;
+}
+
+BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+  BitVector Reserved = getAlwaysReservedRegs();
+
   // Reserve SGPRs.
   //
   unsigned MaxNumSGPRs = ST.getMaxNumSGPRs(MF);
@@ -695,6 +706,7 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
     }
   }
 
+  const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
   Register ScratchRSrcReg = MFI->getScratchRSrcReg();
   if (ScratchRSrcReg != AMDGPU::NoRegister) {
     // Reserve 4 SGPRs for the scratch buffer resource descriptor in case we
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index f3068963fd10f..fa50ca2482554 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -55,6 +55,9 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
   // Second index is 32 different dword offsets.
   static std::array<std::array<uint16_t, 32>, 9> SubRegFromChannelTable;
 
+  static BitVector AlwaysReservedRegs;
+  BitVector getAlwaysReservedRegs() const;
+
   void reserveRegisterTuples(BitVector &, MCRegister Reg) const;
 
 public:

>From 03024666b62e5ce893ed9a7b67ea5d6c668a0dba Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Thu, 20 Mar 2025 12:16:28 +0530
Subject: [PATCH 2/2] Update llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Co-authored-by: Shilei Tian <i at tianshilei.me>
---
 llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 1ab3dbcc97fc3..f98c2f8a6bb33 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -633,9 +633,8 @@ BitVector SIRegisterInfo::AlwaysReservedRegs;
 
 BitVector SIRegisterInfo::getAlwaysReservedRegs() const {
   // Already been calculated, so do not compute again.
-  if (AlwaysReservedRegs.size() == getNumRegs()) {
+  if (AlwaysReservedRegs.size() == getNumRegs())
     return AlwaysReservedRegs;
-  }
 
   BitVector Reserved(getNumRegs());
   Reserved.set(AMDGPU::MODE);