[llvm] [GlobalISel] Combine (sext (trunc x)) to (sext_inreg x) (PR #131622)
Pierre van Houtryve via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 17 07:43:36 PDT 2025
https://github.com/Pierre-vh created https://github.com/llvm/llvm-project/pull/131622
Split from #131312
>From 4dcec18d24b1cd1a0752326abfe44fda6f7447c5 Mon Sep 17 00:00:00 2001
From: pvanhout <pierre.vanhoutryve at amd.com>
Date: Mon, 17 Mar 2025 11:20:00 +0100
Subject: [PATCH] [GlobalISel] Combine (sext (trunc x)) to (sext_inreg x)
Split from #131312
---
.../include/llvm/Target/GlobalISel/Combine.td | 2 +-
.../GlobalISel/CombinerHelperCasts.cpp | 14 +++
.../AMDGPU/GlobalISel/combine-trunc-sext.mir | 117 ++++++++++++++++++
3 files changed, 132 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 3590ab221ad44..660b03080f92e 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -1522,7 +1522,7 @@ def extract_vector_element_build_vector_trunc8 : GICombineRule<
def sext_trunc : GICombineRule<
(defs root:$root, build_fn_matchinfo:$matchinfo),
- (match (G_TRUNC $src, $x, (MIFlags NoSWrap)),
+ (match (G_TRUNC $src, $x),
(G_SEXT $root, $src),
[{ return Helper.matchSextOfTrunc(${root}, ${matchinfo}); }]),
(apply [{ Helper.applyBuildFnMO(${root}, ${matchinfo}); }])>;
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
index 7b4c427a9c504..182484754d091 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
@@ -36,6 +36,20 @@ bool CombinerHelper::matchSextOfTrunc(const MachineOperand &MO,
LLT DstTy = MRI.getType(Dst);
LLT SrcTy = MRI.getType(Src);
+ // Combines without nsw trunc.
+ if (!(Trunc->getFlags() & MachineInstr::NoSWrap)) {
+ if (DstTy != SrcTy)
+ return false;
+
+ unsigned TruncWidth = MRI.getType(Trunc->getReg(0)).getScalarSizeInBits();
+ MatchInfo = [=](MachineIRBuilder &B) {
+ B.buildSExtInReg(Dst, Src, TruncWidth);
+ };
+ return true;
+ }
+
+ // Combines for nsw trunc.
+
if (DstTy == SrcTy) {
MatchInfo = [=](MachineIRBuilder &B) { B.buildCopy(Dst, Src); };
return true;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir
new file mode 100644
index 0000000000000..b2277c4e1141b
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir
@@ -0,0 +1,117 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+
+---
+name: trunc_sext_i32_i16
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; GCN-LABEL: name: trunc_sext_i32_i16
+ ; GCN: liveins: $vgpr0
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
+ ; GCN-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s16) = G_TRUNC %0
+ %2:_(s32) = G_SEXT %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: trunc_sext_i32_i8
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; GCN-LABEL: name: trunc_sext_i32_i8
+ ; GCN: liveins: $vgpr0
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
+ ; GCN-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s8) = G_TRUNC %0
+ %2:_(s32) = G_SEXT %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: trunc_sext_i64_i32
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; GCN-LABEL: name: trunc_sext_i64_i32
+ ; GCN: liveins: $vgpr0_vgpr1
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
+ ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_TRUNC %0
+ %2:_(s64) = G_SEXT %1
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: trunc_sext_v4i32_v4i16
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+ ; GCN-LABEL: name: trunc_sext_v4i32_v4i16
+ ; GCN: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<4 x s32>) = G_SEXT_INREG [[COPY]], 16
+ ; GCN-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[SEXT_INREG]](<4 x s32>)
+ %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(<4 x s16>) = G_TRUNC %0
+ %2:_(<4 x s32>) = G_SEXT %1
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
+...
+
+---
+name: trunc_sext_v4i16_v4i8
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; GCN-LABEL: name: trunc_sext_v4i16_v4i8
+ ; GCN: liveins: $vgpr0_vgpr1
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
+ ; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<4 x s16>) = G_SEXT_INREG [[COPY]], 8
+ ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](<4 x s16>)
+ %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
+ %1:_(<4 x s8>) = G_TRUNC %0
+ %2:_(<4 x s16>) = G_SEXT %1
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: trunc_sext_mismatching_types
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; GCN-LABEL: name: trunc_sext_mismatching_types
+ ; GCN: liveins: $vgpr0_vgpr1
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
+ ; GCN-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16)
+ ; GCN-NEXT: $vgpr0 = COPY [[SEXT]](s32)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s16) = G_TRUNC %0
+ %2:_(s32) = G_SEXT %1
+ $vgpr0 = COPY %2
+...
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