[llvm] [WebAssembly] Add more lowerings for wide-arithmetic (PR #132430)

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git-clang-format --diff b858ba0f6597c66e5c276ca9e2564ca27e7e28e7 9c1219cefaadd333df4d9df88938440654a43f20 --extensions h,cpp -- llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 3a720af1de..7b75bb9250 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -1822,7 +1822,7 @@ SDValue WebAssemblyTargetLowering::LowerMUL_LOHI(SDValue Op,
 // the upper bits of both operands are constant zeros. The upper bits of the
 // result are whether the overflow happened.
 SDValue WebAssemblyTargetLowering::LowerUADDO(SDValue Op,
-                                             SelectionDAG &DAG) const {
+                                              SelectionDAG &DAG) const {
   assert(Subtarget->hasWideArithmetic());
   assert(Op.getValueType() == MVT::i64);
   assert(Op.getOpcode() == ISD::UADDO);
@@ -1831,7 +1831,8 @@ SDValue WebAssemblyTargetLowering::LowerUADDO(SDValue Op,
   SDValue RHS = Op.getOperand(1);
   SDValue Zero = DAG.getConstant(0, DL, MVT::i64);
   SDValue Result =
-      DAG.getNode(WebAssemblyISD::I64_ADD128, DL, DAG.getVTList(MVT::i64, MVT::i64), LHS, Zero, RHS, Zero);
+      DAG.getNode(WebAssemblyISD::I64_ADD128, DL,
+                  DAG.getVTList(MVT::i64, MVT::i64), LHS, Zero, RHS, Zero);
   SDValue CarryI64(Result.getNode(), 1);
   SDValue CarryI32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, CarryI64);
   SDValue Ops[] = {Result, CarryI32};

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https://github.com/llvm/llvm-project/pull/132430