[llvm] 45090b3 - [SLP]Check the whole def-use chain in the tree to find proper dominance, if the last instruction is the same

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2025-03-18T10:01:13-07:00
New Revision: 45090b3059562b32723cd25679db75d1574ab04e

URL: https://github.com/llvm/llvm-project/commit/45090b3059562b32723cd25679db75d1574ab04e
DIFF: https://github.com/llvm/llvm-project/commit/45090b3059562b32723cd25679db75d1574ab04e.diff

LOG: [SLP]Check the whole def-use chain in the tree to find proper dominance, if the last instruction is the same

If the insertion point (last instruction) of the user nodes is the same,
need to check the whole def-use chain in the tree to find proper
dominance to prevent a compiler crash.

Fixes #131818

Added: 
    llvm/test/Transforms/SLPVectorizer/X86/same-last-instruction-different-parents.ll

Modified: 
    llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 24171f1d9a065..4a835bc797ab6 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -14086,11 +14086,18 @@ BoUpSLP::isGatherShuffledSingleRegisterEntry(
   auto CheckParentNodes = [&](const TreeEntry *User1, const TreeEntry *User2,
                               unsigned EdgeIdx) {
     const TreeEntry *Ptr1 = User1;
+    const TreeEntry *Ptr2 = User2;
+    SmallDenseMap<const TreeEntry *, unsigned> PtrToIdx;
+    while (Ptr2) {
+      PtrToIdx.try_emplace(Ptr2, EdgeIdx);
+      EdgeIdx = Ptr2->UserTreeIndex.EdgeIdx;
+      Ptr2 = Ptr2->UserTreeIndex.UserTE;
+    }
     while (Ptr1) {
       unsigned Idx = Ptr1->UserTreeIndex.EdgeIdx;
       Ptr1 = Ptr1->UserTreeIndex.UserTE;
-      if (Ptr1 == User2)
-        return Idx < EdgeIdx;
+      if (auto It = PtrToIdx.find(Ptr1); It != PtrToIdx.end())
+        return Idx < It->second;
     }
     return false;
   };

diff  --git a/llvm/test/Transforms/SLPVectorizer/X86/same-last-instruction-
diff erent-parents.ll b/llvm/test/Transforms/SLPVectorizer/X86/same-last-instruction-
diff erent-parents.ll
new file mode 100644
index 0000000000000..ef75a8dd99169
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/same-last-instruction-
diff erent-parents.ll
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+define i32 @test(i32 %0, i1 %1) {
+; CHECK-LABEL: define i32 @test(
+; CHECK-SAME: i32 [[TMP0:%.*]], i1 [[TMP1:%.*]]) {
+; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i32 0
+; CHECK-NEXT:    [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP5:%.*]] = sitofp <2 x i32> [[TMP4]] to <2 x double>
+; CHECK-NEXT:    [[TMP6:%.*]] = sitofp <2 x i32> [[TMP4]] to <2 x double>
+; CHECK-NEXT:    br i1 [[TMP1]], label %[[BB7:.*]], label %[[BB9:.*]]
+; CHECK:       [[BB7]]:
+; CHECK-NEXT:    [[TMP8:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP6]], <2 x double> zeroinitializer, <2 x double> zeroinitializer)
+; CHECK-NEXT:    br label %[[BB16:.*]]
+; CHECK:       [[BB9]]:
+; CHECK-NEXT:    br i1 false, label %[[BB14:.*]], label %[[BB10:.*]]
+; CHECK:       [[BB10]]:
+; CHECK-NEXT:    [[TMP11:%.*]] = call <2 x double> @llvm.copysign.v2f64(<2 x double> zeroinitializer, <2 x double> [[TMP5]])
+; CHECK-NEXT:    [[TMP12:%.*]] = shufflevector <2 x double> [[TMP6]], <2 x double> <double 0.000000e+00, double poison>, <2 x i32> <i32 2, i32 1>
+; CHECK-NEXT:    [[TMP13:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP11]], <2 x double> [[TMP12]], <2 x double> zeroinitializer)
+; CHECK-NEXT:    br label %[[BB14]]
+; CHECK:       [[BB14]]:
+; CHECK-NEXT:    [[TMP15:%.*]] = phi <2 x double> [ [[TMP13]], %[[BB10]] ], [ zeroinitializer, %[[BB9]] ]
+; CHECK-NEXT:    br label %[[BB16]]
+; CHECK:       [[BB16]]:
+; CHECK-NEXT:    [[TMP17:%.*]] = phi <2 x double> [ [[TMP15]], %[[BB14]] ], [ [[TMP8]], %[[BB7]] ]
+; CHECK-NEXT:    [[TMP18:%.*]] = extractelement <2 x double> [[TMP17]], i32 0
+; CHECK-NEXT:    [[TMP19:%.*]] = extractelement <2 x double> [[TMP17]], i32 1
+; CHECK-NEXT:    [[TMP20:%.*]] = fmul double [[TMP19]], [[TMP18]]
+; CHECK-NEXT:    [[TMP21:%.*]] = fptosi double [[TMP20]] to i32
+; CHECK-NEXT:    ret i32 [[TMP21]]
+;
+  %3 = sitofp i32 %0 to double
+  %4 = sitofp i32 %0 to double
+  %5 = sitofp i32 %0 to double
+  br i1 %1, label %6, label %9
+
+6:
+  %7 = tail call double @llvm.fmuladd.f64(double %4, double 0.000000e+00, double 0.000000e+00)
+  %8 = tail call double @llvm.fmuladd.f64(double %5, double 0.000000e+00, double 0.000000e+00)
+  br label %18
+
+9:
+  br i1 false, label %15, label %10
+
+10:
+  %11 = call double @llvm.copysign.f64(double 0.000000e+00, double %3)
+  %12 = tail call double @llvm.fmuladd.f64(double %11, double %4, double 0.000000e+00)
+  %13 = call double @llvm.copysign.f64(double 0.000000e+00, double %5)
+  %14 = tail call double @llvm.fmuladd.f64(double %13, double 0.000000e+00, double 0.000000e+00)
+  br label %15
+
+15:
+  %16 = phi double [ %12, %10 ], [ 0.000000e+00, %9 ]
+  %17 = phi double [ %14, %10 ], [ 0.000000e+00, %9 ]
+  br label %18
+
+18:
+  %19 = phi double [ %17, %15 ], [ %8, %6 ]
+  %20 = phi double [ %16, %15 ], [ %7, %6 ]
+  %21 = fmul double %20, %19
+  %22 = fptosi double %21 to i32
+  ret i32 %22
+}