[llvm] [SelectionDAG][RISCV] Avoid store merging across function calls (PR #130430)

[Mikhail R. Gadelha via llvm-commits]

mikhailramalho wrote:

> I chatted a bit with @mikhailramalho offline, just recording the key bits.
> 
> 1. As mentioned by Luke above, we probably want to avoid inhibiting scalar merging.  Similarly, if we already have two small vectors combining into one larger vector is probably at least neutral.  (These are RISCV specific profitability statements.)
> 2. I would expect to see something in the check in terms of the callee saved registers for the callee of the call.  The _reason_ that scalar to vector merging is likely unprofitable is that we have scalar CSRs in the standard calling convention, but do not have vector CSRs.
> 3. A minimal patch might simply check if the proposed merged type has any CSRs.  That would cover the most painful case today.  A more complicate heuristic would try to reason about whether the merged type was a different register class than the source types, and then apply the CSR check.  We could get fancy when both register classes have CSRs, but the destination has fewer, but I suggest we defer that case until someone has an example which cares.
> 4. We do appear to have calls to getRegClassFor in DAGCombine already, so that knowledge should be available.  I don't see us currently using information about the calling convention in this code, hopefully that's available?  I haven't checked.
> 
> Edit: Re-reading this, I think I may have accidental mislead here. We could have the callee saved heuristic in DAG as mentioned, but we could also just extend the TLI hook you added slightly to have the source type, and have this reasoning explained in a comment in the hook. The result is static for the target.

I mentioned earlier to have this as a follow-up patch but maybe it's a small change and we can fit in this PR? I'll take a look at how to extend the TLI hook to check for callee save regs


https://github.com/llvm/llvm-project/pull/130430