[llvm] [AArch64][SVE] Add dot product lowering for PARTIAL_REDUCE_MLA node (PR #130933)

[Benjamin Maxwell via llvm-commits]

================
@@ -1585,6 +1585,21 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::MSTORE, VT, Custom);
     }
 
+    for (MVT VT : MVT::integer_scalable_vector_valuetypes()) {
+      if (!EnablePartialReduceNodes)
+        break;
+      for (MVT InnerVT : MVT::integer_scalable_vector_valuetypes()) {
+        ElementCount VTElemCount = VT.getVectorElementCount();
+        if (VTElemCount.getKnownMinValue() == 1)
+          continue;
+        if (VTElemCount * 4 == InnerVT.getVectorElementCount())
+          setPartialReduceMLAAction(VT, InnerVT, Custom);
+        if (InnerVT.getVectorElementType().getSizeInBits() * 4 ==
+            VT.getVectorElementType().getSizeInBits())
+          setPartialReduceMLAAction(VT, InnerVT, Legal);
+      }
+    }
----------------
MacDue wrote:

My understanding is the actual number of type combinations where we would do something special is actually quite small, e.g. something like:
```
// These are lowered directly to UDOT/SDOT.
setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv8i16, Legal);
setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv16i8, Legal);

// These can be lowered to wide adds in LowerOperation.
setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv4i32, Custom);
setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv8i16, Custom);
setPartialReduceMLAAction(MVT::nxv8i16, MVT::nxv16i8, Custom);
```

https://github.com/llvm/llvm-project/pull/130933