[clang] [llvm] [RISCV] Remove experimental from Sdext and Sdtrig which are ratified. (PR #132529)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 23 20:35:53 PDT 2025
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/132529
>From 3b30343a99ecb7095adb734be2e3e71a67a597ac Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 21 Mar 2025 23:35:56 -0700
Subject: [PATCH 1/2] [RISCV] Remove experimental from Sdext and Sdtrig which
are ratified.
They were ratified in February 2025.
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++--
llvm/test/CodeGen/RISCV/attributes.ll | 4 ++--
llvm/test/CodeGen/RISCV/features-info.ll | 4 ++--
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 4 ++--
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index c1223beb304ad..d7edf94565ff4 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -869,9 +869,9 @@ def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
// Supervisor extensions
-def FeatureStdExtSdext : RISCVExperimentalExtension<1, 0, "External debugger">;
+def FeatureStdExtSdext : RISCVExtension<1, 0, "External debugger">;
-def FeatureStdExtSdtrig : RISCVExperimentalExtension<1, 0, "Debugger triggers">;
+def FeatureStdExtSdtrig : RISCVExtension<1, 0, "Debugger triggers">;
def FeatureStdExtShgatpa
: RISCVExtension<1, 0,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index cc2ce1a572d9a..ea8f35957c046 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -311,8 +311,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV64SMCTR %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV64SSCTR %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
+; RUN: llc -mtriple=riscv64 -mattr=+sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s
+; RUN: llc -mtriple=riscv64 -mattr=+sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-xqccmp %s -o - | FileCheck --check-prefix=RV64XQCCMP %s
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index ff29777a3ec37..60c29622b520a 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -15,8 +15,6 @@
; CHECK: e - 'E' (Embedded Instruction Set with 16 GPRs).
; CHECK: experimental - Experimental intrinsics.
; CHECK: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile.
-; CHECK: experimental-sdext - 'Sdext' (External debugger).
-; CHECK: experimental-sdtrig - 'Sdtrig' (Debugger triggers).
; CHECK: experimental-smctr - 'Smctr' (Control Transfer Records Machine Level).
; CHECK: experimental-ssctr - 'Ssctr' (Control Transfer Records Supervisor Level).
; CHECK: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses).
@@ -96,6 +94,8 @@
; CHECK: rvi20u32 - RISC-V rvi20u32 profile.
; CHECK: rvi20u64 - RISC-V rvi20u64 profile.
; CHECK: save-restore - Enable save/restore..
+; CHECK: sdext - 'Sdext' (External debugger).
+; CHECK: sdtrig - 'Sdtrig' (Debugger triggers).
; CHECK: sha - 'Sha' (Augmented Hypervisor).
; CHECK: shcounterenw - 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero).
; CHECK: shgatpa - 'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare).
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 16876ebcf9f83..f916f06827e03 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1058,6 +1058,8 @@ R"(All available -march extensions for RISC-V
zvl8192b 1.0
zhinx 1.0
zhinxmin 1.0
+ sdext 1.0
+ sdtrig 1.0
sha 1.0
shcounterenw 1.0
shgatpa 1.0
@@ -1137,8 +1139,6 @@ Experimental extensions
zvbc32e 0.7
zvkgs 0.7
zvqdotq 0.0
- sdext 1.0
- sdtrig 1.0
smctr 1.0
ssctr 1.0
svukte 0.3
>From 8cefd3b15efa49deecd53e76618862622ea3dfec Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sun, 23 Mar 2025 20:34:27 -0700
Subject: [PATCH 2/2] fixup! Update print-supported-extensions-riscv.c
---
clang/test/Driver/print-supported-extensions-riscv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index b5533b54347b9..7e201b1149ec3 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -112,6 +112,8 @@
// CHECK-NEXT: zvl8192b 1.0 'Zvl8192b' (Minimum Vector Length 8192)
// CHECK-NEXT: zhinx 1.0 'Zhinx' (Half Float in Integer)
// CHECK-NEXT: zhinxmin 1.0 'Zhinxmin' (Half Float in Integer Minimal)
+// CHECK-NEXT: sdext 1.0 'Sdext' (External debugger)
+// CHECK-NEXT: sdtrig 1.0 'Sdtrig' (Debugger triggers)
// CHECK-NEXT: sha 1.0 'Sha' (Augmented Hypervisor)
// CHECK-NEXT: shcounterenw 1.0 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero)
// CHECK-NEXT: shgatpa 1.0 'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)
@@ -191,8 +193,6 @@
// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
// CHECK-NEXT: zvqdotq 0.0 'Zvqdotq' (Vector quad widening 4D Dot Product)
-// CHECK-NEXT: sdext 1.0 'Sdext' (External debugger)
-// CHECK-NEXT: sdtrig 1.0 'Sdtrig' (Debugger triggers)
// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
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