[llvm] [RISCV] Move RISCVVMV0Elimination past pre-ra scheduling (PR #132057)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

For some regressions, I don't know if they are related to a reg pressure set limit issue I have been looking at for a long time (but I was occupied by other urgent issues so I haven't fixed it :-( ).
The current reg pressure set limit is:
```cpp
// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned RISCVGenRegisterInfo::
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
  static const uint8_t PressureLimitTable[] = {
    2,  	// 0: GPRC_and_SR07
    2,  	// 1: GPRX0
    2,  	// 2: SP
    2,  	// 3: GPRX7
    3,  	// 4: GPRX1
    8,  	// 5: FPR16C
    8,  	// 6: GPRF16C
    8,  	// 7: SR07
    8,  	// 8: VMV0
    14,  	// 9: GPRF16C_with_SR07
    16,  	// 10: GPRTC
    24,  	// 11: VRM8NoV0
    32,  	// 12: FPR16
    32,  	// 13: VM
    33,  	// 14: GPRAll
  };
  return PressureLimitTable[Idx];
}
```
Apparently, the limit 8 of `VMV0` is not right since there is only one register in it. But if we override `getRegPressureSetLimit` in `RISCVInstrInfo` and returns 1 or 2 for `VMV0`, we may meet similar problem in RA (`out of registers`). But I encourage you to try this way. :-)

Anyway, I really appreciate this work and am looking forward to make it go farther!

https://github.com/llvm/llvm-project/pull/132057