[llvm] [AMDGPU][True16][CodeGen]disable true16 on fneg test (PR #132221)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 20 07:32:23 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Brox Chen (broxigarchen)
<details>
<summary>Changes</summary>
This is a NFC change.
Revert the failed test case in https://github.com/llvm/llvm-project/pull/131206
---
Patch is 221.20 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/132221.diff
1 Files Affected:
- (modified) llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll (+932-1747)
``````````diff
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
index 5ea39997938ad..cdb31534674de 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
@@ -5,9 +5,10 @@
; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope --check-prefixes=VI,VI-SAFE %s
; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope --check-prefixes=VI,VI-NSZ %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-SAFE,GFX11-SAFE-TRUE16 %s
+; FIXME-TRUE16. fix true16 test
+; XUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-SAFE,GFX11-SAFE-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-SAFE,GFX11-SAFE-FAKE16 %s
-; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-NSZ,GFX11-NSZ-TRUE16 %s
+; XUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-NSZ,GFX11-NSZ-TRUE16 %s
; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-NSZ,GFX11-NSZ-FAKE16 %s
; --------------------------------------------------------------------------------
@@ -49,6 +50,19 @@ define half @v_fneg_add_f16(half %a, half %b) #0 {
; VI-NSZ-NEXT: v_sub_f16_e64 v0, -v0, v1
; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-SAFE-LABEL: v_fneg_add_f16:
+; GFX11-SAFE: ; %bb.0:
+; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SAFE-NEXT: v_add_f16_e32 v0, v0, v1
+; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-NSZ-LABEL: v_fneg_add_f16:
+; GFX11-NSZ: ; %bb.0:
+; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NSZ-NEXT: v_sub_f16_e64 v0, -v0, v1
+; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_f16:
; GFX11-SAFE-TRUE16: ; %bb.0:
; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -56,26 +70,11 @@ define half @v_fneg_add_f16(half %a, half %b) #0 {
; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: v_fneg_add_f16:
-; GFX11-SAFE-FAKE16: ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e32 v0, v0, v1
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_f16:
; GFX11-NSZ-TRUE16: ; %bb.0:
; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e64 v0.l, -v0.l, v1.l
; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: v_fneg_add_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e64 v0, -v0, v1
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%add = fadd half %a, %b
%fneg = fneg half %add
ret half %fneg
@@ -100,6 +99,13 @@ define { half, half } @v_fneg_add_store_use_add_f16(half %a, half %b) #0 {
; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: v_fneg_add_store_use_add_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_f16_e32 v1, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_store_use_add_f16:
; GFX11-SAFE-TRUE16: ; %bb.0:
; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -107,15 +113,6 @@ define { half, half } @v_fneg_add_store_use_add_f16(half %a, half %b) #0 {
; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v1.l
; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: v_fneg_add_store_use_add_f16:
-; GFX11-SAFE-FAKE16: ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e32 v1, v0, v1
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v1
-; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_store_use_add_f16:
; GFX11-NSZ-TRUE16: ; %bb.0:
; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -123,14 +120,6 @@ define { half, half } @v_fneg_add_store_use_add_f16(half %a, half %b) #0 {
; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v1.l
; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: v_fneg_add_store_use_add_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e32 v1, v0, v1
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v1
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%add = fadd half %a, %b
%fneg = fneg half %add
%insert.0 = insertvalue { half, half } poison, half %fneg, 0
@@ -177,6 +166,22 @@ define { half, half } @v_fneg_add_multi_use_add_f16(half %a, half %b) #0 {
; VI-NSZ-NEXT: v_mul_f16_e32 v1, -4.0, v0
; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-SAFE-LABEL: v_fneg_add_multi_use_add_f16:
+; GFX11-SAFE: ; %bb.0:
+; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SAFE-NEXT: v_add_f16_e32 v1, v0, v1
+; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v1
+; GFX11-SAFE-NEXT: v_mul_f16_e32 v1, 4.0, v1
+; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-NSZ-LABEL: v_fneg_add_multi_use_add_f16:
+; GFX11-NSZ: ; %bb.0:
+; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NSZ-NEXT: v_sub_f16_e64 v0, -v0, v1
+; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NSZ-NEXT: v_mul_f16_e32 v1, -4.0, v0
+; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_multi_use_add_f16:
; GFX11-SAFE-TRUE16: ; %bb.0:
; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -185,16 +190,6 @@ define { half, half } @v_fneg_add_multi_use_add_f16(half %a, half %b) #0 {
; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.h
; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v1.l, 4.0, v0.h
; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: v_fneg_add_multi_use_add_f16:
-; GFX11-SAFE-FAKE16: ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e32 v1, v0, v1
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v1
-; GFX11-SAFE-FAKE16-NEXT: v_mul_f16_e32 v1, 4.0, v1
-; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_multi_use_add_f16:
; GFX11-NSZ-TRUE16: ; %bb.0:
; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -202,14 +197,6 @@ define { half, half } @v_fneg_add_multi_use_add_f16(half %a, half %b) #0 {
; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v1.l, -4.0, v0.l
; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: v_fneg_add_multi_use_add_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e64 v0, -v0, v1
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_mul_f16_e32 v1, -4.0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%add = fadd half %a, %b
%fneg = fneg half %add
%use1 = fmul half %add, 4.0
@@ -254,6 +241,19 @@ define half @v_fneg_add_fneg_x_f16(half %a, half %b) #0 {
; VI-NSZ-NEXT: v_sub_f16_e32 v0, v0, v1
; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-SAFE-LABEL: v_fneg_add_fneg_x_f16:
+; GFX11-SAFE: ; %bb.0:
+; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SAFE-NEXT: v_sub_f16_e32 v0, v1, v0
+; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-NSZ-LABEL: v_fneg_add_fneg_x_f16:
+; GFX11-NSZ: ; %bb.0:
+; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NSZ-NEXT: v_sub_f16_e32 v0, v0, v1
+; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_fneg_x_f16:
; GFX11-SAFE-TRUE16: ; %bb.0:
; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -261,26 +261,11 @@ define half @v_fneg_add_fneg_x_f16(half %a, half %b) #0 {
; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: v_fneg_add_fneg_x_f16:
-; GFX11-SAFE-FAKE16: ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v0, v1, v0
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_fneg_x_f16:
; GFX11-NSZ-TRUE16: ; %bb.0:
; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: v_fneg_add_fneg_x_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
%add = fadd half %fneg.a, %b
%fneg = fneg half %add
@@ -322,6 +307,19 @@ define half @v_fneg_add_x_fneg_f16(half %a, half %b) #0 {
; VI-NSZ-NEXT: v_sub_f16_e32 v0, v1, v0
; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-SAFE-LABEL: v_fneg_add_x_fneg_f16:
+; GFX11-SAFE: ; %bb.0:
+; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SAFE-NEXT: v_sub_f16_e32 v0, v0, v1
+; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-NSZ-LABEL: v_fneg_add_x_fneg_f16:
+; GFX11-NSZ: ; %bb.0:
+; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NSZ-NEXT: v_sub_f16_e32 v0, v1, v0
+; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_x_fneg_f16:
; GFX11-SAFE-TRUE16: ; %bb.0:
; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -329,26 +327,11 @@ define half @v_fneg_add_x_fneg_f16(half %a, half %b) #0 {
; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: v_fneg_add_x_fneg_f16:
-; GFX11-SAFE-FAKE16: ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_x_fneg_f16:
; GFX11-NSZ-TRUE16: ; %bb.0:
; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v1.l, v0.l
; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: v_fneg_add_x_fneg_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v0, v1, v0
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fneg.b = fneg half %b
%add = fadd half %a, %fneg.b
%fneg = fneg half %add
@@ -390,6 +373,19 @@ define half @v_fneg_add_fneg_fneg_f16(half %a, half %b) #0 {
; VI-NSZ-NEXT: v_add_f16_e32 v0, v0, v1
; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-SAFE-LABEL: v_fneg_add_fneg_fneg_f16:
+; GFX11-SAFE: ; %bb.0:
+; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SAFE-NEXT: v_sub_f16_e64 v0, -v0, v1
+; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-NSZ-LABEL: v_fneg_add_fneg_fneg_f16:
+; GFX11-NSZ: ; %bb.0:
+; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NSZ-NEXT: v_add_f16_e32 v0, v0, v1
+; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_fneg_fneg_f16:
; GFX11-SAFE-TRUE16: ; %bb.0:
; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -397,26 +393,11 @@ define half @v_fneg_add_fneg_fneg_f16(half %a, half %b) #0 {
; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: v_fneg_add_fneg_fneg_f16:
-; GFX11-SAFE-FAKE16: ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e64 v0, -v0, v1
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_fneg_fneg_f16:
; GFX11-NSZ-TRUE16: ; %bb.0:
; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: v_fneg_add_fneg_fneg_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e32 v0, v0, v1
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
%fneg.b = fneg half %b
%add = fadd half %fneg.a, %fneg.b
@@ -465,6 +446,24 @@ define { half, half } @v_fneg_add_store_use_fneg_x_f16(half %a, half %b) #0 {
; VI-NSZ-NEXT: v_mov_b32_e32 v1, v2
; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-SAFE-LABEL: v_fneg_add_store_use_fneg_x_f16:
+; GFX11-SAFE: ; %bb.0:
+; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SAFE-NEXT: v_sub_f16_e32 v1, v1, v0
+; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SAFE-NEXT: v_xor_b32_e32 v2, 0x8000, v1
+; GFX11-SAFE-NEXT: v_xor_b32_e32 v1, 0x8000, v0
+; GFX11-SAFE-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-NSZ-LABEL: v_fneg_add_store_use_fneg_x_f16:
+; GFX11-NSZ: ; %bb.0:
+; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NSZ-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX11-NSZ-NEXT: v_xor_b32_e32 v1, 0x8000, v0
+; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NSZ-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_store_use_fneg_x_f16:
; GFX11-SAFE-TRUE16: ; %bb.0:
; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -474,17 +473,6 @@ define { half, half } @v_fneg_add_store_use_fneg_x_f16(half %a, half %b) #0 {
; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: v_fneg_add_store_use_fneg_x_f16:
-; GFX11-SAFE-FAKE16: ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v1, v1, v0
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v2, 0x8000, v1
-; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v1, 0x8000, v0
-; GFX11-SAFE-FAKE16-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_store_use_fneg_x_f16:
; GFX11-NSZ-TRUE16: ; %bb.0:
; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -493,15 +481,6 @@ define { half, half } @v_fneg_add_store_use_fneg_x_f16(half %a, half %b) #0 {
; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.h, v1.l
; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: v_fneg_add_store_use_fneg_x_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v2, v0, v1
-; GFX11-NSZ-FAKE16-NEXT: v_xor_b32_e32 v1, 0x8000, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-FAKE16-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
%add = fadd half %fneg.a, %b
%fneg = fneg half %add
@@ -557,6 +536,24 @@ define { half, half } @v_fneg_add_multi_use_fneg_x_f16(half %a, half %b, half %c
; VI-NSZ-NEXT: v_mov_b32_e32 v0, v3
; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-SAFE-LABEL: v_fneg_add_multi_use_fneg_x_f16:
+; GFX11-SAFE: ; %bb.0:
+; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SAFE-NEXT: v_sub_f16_e32 v1, v1, v0
+; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SAFE-NEXT: v_xor_b32_e32 v3, 0x8000, v1
+; GFX11-SAFE-NEXT: v_mul_f16_e64 v1, -v0, v2
+; GFX11-SAFE-NEXT: v_mov_b32_e32 v0, v3
+; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-NSZ-LABEL: v_fneg_add_multi_use_fneg_x_f16:
+; GFX11-NSZ: ; %bb.0:
+; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NSZ-NEXT: v_sub_f16_e32 v3, v0, v1
+; GFX11-NSZ-NEXT: v_mul_f16_e64 v1, -v0, v2
+; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NSZ-NEXT: v_mov_b32_e32 v0, v3
+; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_multi_use_fneg_x_f16:
; GFX11-SAFE-TRUE16: ; %bb.0:
; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -566,17 +563,6 @@ define { half, half } @v_fneg_add_multi_use_fneg_x_f16(half %a, half %b, half %c
; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v1.l, -v0.h, v2.l
; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: v_fneg_add_multi_use_fneg_x_f16:
-; GFX11-SAFE-FAKE16: ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v1, v1, v0
-; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v3, 0x8000, v1
-; GFX11-SAFE-FAKE16-NEXT: v_mul_f16_e64 v1, -v0, v2
-; GFX11-SAFE-FAKE16-NEXT: v_mov_b32_e32 v0, v3
-; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_multi_use_fneg_x_f16:
; GFX11-NSZ-TRUE16: ; %bb.0:
; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -585,15 +571,6 @@ define { half, half } @v_fneg_add_multi_use_fneg_x_f16(half %a, half %b, half %c
; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.h, v1.l
; GFX11-NS...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/132221
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