[llvm] [NVPTX] Improve 64bit FSH/ROT lowering when shift amount is constant (PR #131371)

[Alex MacLean via llvm-commits]

AlexMaclean wrote:

> Can you add an additional section to your PR description where you describe why we need new `NVPTXISD` nodes to handle this case and under what conditions we can begin using `ISD` nodes and perhaps even port this to `LegalizeDAG`?

Added, also added a comment in the code.

> Also, which test case is the regression?

Every test case that changed show improvement. For example, in llvm/test/CodeGen/NVPTX/rotate_64.ll, `@rotate64` previously had 3 64-bit operations and now has 2 32-bit operations.


https://github.com/llvm/llvm-project/pull/131371