[llvm] [RISCV] Move RISCVVMV0Elimination past pre-ra scheduling (PR #132057)

[Philip Reames via llvm-commits]

preames wrote:

> 3\. We need to handle subregisters now whereas previously they didn't seem to show up

I went and looked into this.  The one and only case in check-llvm is the following:
```
  (function entry)
  %0:vrm2_with_sub_vrm1_0_in_vmv0 = COPY $v8m2
  ...
  %15:vrm8nov0 = PseudoVMERGE_VIM_M8 undef %15:vrm8nov0(tied-def 0), %12:vrm8, 1, %0.sub_vrm1_0:vrm2_with_sub_vrm1_0_in_vmv0, -1, 3
```
There doesn't seem to be anything too oddly specific about @foo from test/CodeGen/RISCV/rvv/pr88576.ll (which is where this came from).  This looks correct (i.e. is a valid subreg usage).  It is interesting that the use of the subregister bit ends up so narrow here.  Tracing through print-after-all, it looks like RegisterCoalescer eliminates a copy and creates the sub-register use.  


https://github.com/llvm/llvm-project/pull/132057