[llvm] [AArch64] A simple tool for generating a scheduling model draft from a SWOG (PR #131525)

[via llvm-commits]

FLZ101 wrote:


> I came across this old review for a X86 CPU: https://reviews.llvm.org/D130897. I have also not yet studied that in detail, but there seems to be a lot more going on in that patch.

The tool in this PR is much simpler since it only generates a draft rather than a working sched model. It does that based on a simple rule: for each row in the instruction tables, match the throughput assuming all utilized units are fully utilized.

Take the following row in the Neoverse N3 instruction tables as an example:

```
Instruction Group           Instructions  Latency  Throughput  Pipelines
Branch and link, register   BLR           1        2           B, S
```

The throughput is 2, that means 2 instructions are executed in a cycle. The pipeline B and C each has 2 units, that means 2 B uops and 2 S uops are executed in a cycle. So each instruction has 1 B uop and 1 S uop.

For any instructions the above rule does not applies to, we need to manually modify their descriptions.

It does not map instruction names in SWOG to names in LLVM. 

It does not define any forwarding rules.


https://github.com/llvm/llvm-project/pull/131525