[llvm] [X86] Prevent APX NDD compression when it creates a partial write (PR #132051)

[Phoebe Wang via llvm-commits]

================
@@ -6793,19 +6793,43 @@ static bool hasPartialRegUpdate(unsigned Opcode, const X86Subtarget &Subtarget,
 unsigned X86InstrInfo::getPartialRegUpdateClearance(
     const MachineInstr &MI, unsigned OpNum,
     const TargetRegisterInfo *TRI) const {
-  if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
+
+  if (OpNum != 0)
+    return 0;
+
+  // With the NDD/ZU features, ISel may generate NDD/ZU ops which
+  // appear to perform partial writes. We detect these based on flags
+  // and register class.
+  bool HasNDDPartialWrite = false;
+  if (X86II::hasNewDataDest(MI.getDesc().TSFlags)) {
+    Register Reg = MI.getOperand(0).getReg();
+    if (Reg.isVirtual()) {
+      auto &MRI = MI.getParent()->getParent()->getRegInfo();
+      if (auto *TRC = MRI.getRegClassOrNull(Reg))
+        HasNDDPartialWrite = (TRC->getID() == X86::GR16RegClassID ||
+                              TRC->getID() == X86::GR8RegClassID);
+    } else
+      HasNDDPartialWrite =
+          X86::GR8RegClass.contains(Reg) || X86::GR16RegClass.contains(Reg);
+  }
----------------
phoebewang wrote:

```suggestion
  bool IsND = X86II::hasNewDataDest(MI.getDesc().TSFlags);
  Register Reg = MI.getOperand(0).getReg();
  if (IsND) {
    if (Reg.isVirtual())
      return 0;
    HasNDDPartialWrite = X86::GR8RegClass.contains(Reg) || X86::GR16RegClass.contains(Reg);
  }
```

https://github.com/llvm/llvm-project/pull/132051