[llvm] [RISCV] Correct qc.e.li instruction definition (PR #132380)

[Sudharsan Veeravalli via llvm-commits]

https://github.com/svs-quic created https://github.com/llvm/llvm-project/pull/132380

The instruction has no tied operands. It was incorrectly using QCIRVInstEAI which has a tied operand for the destination register.

>From aa98d9dfe849d8593b8431a0a0958e557aa785f2 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: Fri, 21 Mar 2025 17:36:36 +0530
Subject: [PATCH] [RISCV] Correct qc.e.li instruction definition

It was incorrectly using QCIRVInstEAI which has a tied operand for
the destination register.
---
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index c009bd3b24682..86d31937ab7a2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -726,7 +726,16 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
     let Inst{15-12} = imm20{18-15};
   }
 
-  def QC_E_LI : QCIRVInstEAI<0b000, 0b0, "qc.e.li">;
+  def QC_E_LI : RVInst48<(outs GPRNoX0:$rd), (ins simm32:$imm),
+                         "qc.e.li", "$rd, $imm", [], InstFormatOther> {
+    bits<5> rd;
+    bits<32> imm;
+
+    let Inst{47-16} = imm;
+    let Inst{15-12} = 0b0000;
+    let Inst{11-7} = rd;
+    let Inst{6-0} = 0b0011111;
+  }
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 } // Predicates = [HasVendorXqcili, IsRV32]