[llvm] [RISCV] Rename some DecoderNamespaces and cleanup debug messages. NFC (PR #131409)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 17 10:04:58 PDT 2025
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/131409
>From d30c6045bfe105f9b076c6f871c9ead0dd49eb4d Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 14 Mar 2025 17:31:24 -0700
Subject: [PATCH 1/2] [RISCV] Rename some DecoderNamespaces and cleanup debug
messages. NFC
Rename RISCV32GPRPair and RISCV32Only_ to RV32Only. This gives a
more natural home for the P extension RV32 conflicts.
While I was there I made some improvements to the debug messages.
---
.../RISCV/Disassembler/RISCVDisassembler.cpp | 18 ++++++++----------
llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 10 +++++-----
llvm/lib/Target/RISCV/RISCVInstrInfoD.td | 2 +-
llvm/lib/Target/RISCV/RISCVInstrInfoZa.td | 2 +-
4 files changed, 15 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index f979af4cbe999..0c8e926afbce8 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -690,12 +690,10 @@ static constexpr DecoderListEntry DecoderList32[]{
{DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
{DecoderTableXqci32, XqciFeatureGroup, "Qualcomm uC Extensions"},
{DecoderTableXRivos32, XRivosFeatureGroup, "Rivos"},
- {DecoderTable32, {}, "RISCV32"},
- {DecoderTableRV32GPRPair32, {}, "RV32GPRPair (rv32 and GPR pairs)"},
+ {DecoderTable32, {}, "standard 32-bit instructions"},
+ {DecoderTableRV32Only32, {}, "RV32-only standard instructions"},
{DecoderTableZfinx32, {}, "Zfinx (Float in Integer)"},
- {DecoderTableZdinxRV32GPRPair32,
- {},
- "ZdinxRV32GPRPair (rv32 and Double in Integer)"},
+ {DecoderTableZdinxRV32Only32, {}, "RV32-only Zdinx (Double in Integer)"},
};
DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
@@ -714,7 +712,7 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
continue;
- LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << "table:\n");
+ LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
DecodeStatus Result =
decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
if (Result == MCDisassembler::Fail)
@@ -728,16 +726,16 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
static constexpr DecoderListEntry DecoderList16[]{
// Vendor Extensions
- {DecoderTableXqci16, XqciFeatureGroup, "Qualcomm uC 16bit"},
+ {DecoderTableXqci16, XqciFeatureGroup, "Qualcomm uC 16-bit"},
{DecoderTableXqccmp16,
{RISCV::FeatureVendorXqccmp},
"Xqccmp (Qualcomm 16-bit Push/Pop & Double Move Instructions)"},
{DecoderTableXwchc16, {RISCV::FeatureVendorXwchc}, "WCH QingKe XW"},
// Standard Extensions
// DecoderTableZicfiss16 must be checked before DecoderTable16.
- {DecoderTableZicfiss16, {}, "RVZicfiss (Shadow Stack)"},
- {DecoderTable16, {}, "RISCV_C (16-bit Instruction)"},
- {DecoderTableRISCV32Only_16, {}, "RISCV32Only_16 (16-bit Instruction)"},
+ {DecoderTableZicfiss16, {}, "Zicfiss (Shadow Stack 16-bit)"},
+ {DecoderTable16, {}, "standard 16-bit Instructions"},
+ {DecoderTableRV32Only16, {}, "RV32-only 16-bit Instructions"},
// Zc* instructions incompatible with Zcf or Zcd
{DecoderTableZcOverlap16,
{},
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index 41ed253f2f36d..19f694af071a3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -332,7 +332,7 @@ def C_LW_INX : CLoad_ri<0b010, "c.lw", GPRF32C, uimm7_lsb00>,
let Inst{5} = imm{6};
}
-let DecoderNamespace = "RISCV32Only_",
+let DecoderNamespace = "RV32Only",
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
def C_FLW : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00>,
Sched<[WriteFLD32, ReadFMemBase]> {
@@ -375,7 +375,7 @@ def C_SW_INX : CStore_rri<0b110, "c.sw", GPRF32C, uimm7_lsb00>,
let Inst{5} = imm{6};
}
-let DecoderNamespace = "RISCV32Only_",
+let DecoderNamespace = "RV32Only",
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
def C_FSW : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>,
Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {
@@ -415,7 +415,7 @@ def PseudoC_ADDI_NOP : Pseudo<(outs GPRX0:$rd), (ins GPRX0:$rs1, immzero:$imm),
[], "c.addi", "$rd, $imm">;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1,
- DecoderNamespace = "RISCV32Only_", Defs = [X1],
+ DecoderNamespace = "RV32Only", Defs = [X1],
Predicates = [HasStdExtCOrZca, IsRV32] in
def C_JAL : RVInst16CJ<0b001, 0b01, (outs), (ins simm12_lsb0:$offset),
"c.jal", "$offset">, Sched<[WriteJal]>;
@@ -521,7 +521,7 @@ def C_LWSP_INX : CStackLoad<0b010, "c.lwsp", GPRF32NoX0, uimm8_lsb00>,
let Inst{3-2} = imm{7-6};
}
-let DecoderNamespace = "RISCV32Only_",
+let DecoderNamespace = "RV32Only",
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
def C_FLWSP : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00>,
Sched<[WriteFLD32, ReadFMemBase]> {
@@ -581,7 +581,7 @@ def C_SWSP_INX : CStackStore<0b110, "c.swsp", GPRF32, uimm8_lsb00>,
let Inst{8-7} = imm{7-6};
}
-let DecoderNamespace = "RISCV32Only_",
+let DecoderNamespace = "RV32Only",
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
def C_FSWSP : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00>,
Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
index 89254940a87f4..5a0adeadf35f7 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -62,7 +62,7 @@ def DExt : ExtInfo<"", "", [HasStdExtD], f64, FPR64, FPR32, FPR64, ?>;
def ZdinxExt : ExtInfo<"_INX", "Zfinx", [HasStdExtZdinx, IsRV64],
f64, FPR64INX, FPR32INX, FPR64INX, ?>;
-def Zdinx32Ext : ExtInfo<"_IN32X", "ZdinxRV32GPRPair", [HasStdExtZdinx, IsRV32],
+def Zdinx32Ext : ExtInfo<"_IN32X", "ZdinxRV32Only", [HasStdExtZdinx, IsRV32],
f64, FPR64IN32X, FPR32INX, FPR64IN32X, ?>;
defvar DExts = [DExt, ZdinxExt, Zdinx32Ext];
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
index e903df4d91933..77692f7cd3bee 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
@@ -59,7 +59,7 @@ let Predicates = [HasStdExtZacas], IsSignExtendingOpW = 1 in {
defm AMOCAS_W : AMO_cas_aq_rl<0b00101, 0b010, "amocas.w", GPR>;
} // Predicates = [HasStdExtZacas]
-let Predicates = [HasStdExtZacas, IsRV32], DecoderNamespace = "RV32GPRPair" in {
+let Predicates = [HasStdExtZacas, IsRV32], DecoderNamespace = "RV32Only" in {
defm AMOCAS_D_RV32 : AMO_cas_aq_rl<0b00101, 0b011, "amocas.d", GPRPairRV32>;
} // Predicates = [HasStdExtZacas, IsRV32]
>From ab637eef961e6371f17c374a22f7b36aadf3d800 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 17 Mar 2025 10:04:36 -0700
Subject: [PATCH 2/2] fixup! address comments
---
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 0c8e926afbce8..081101fca7c23 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -691,7 +691,7 @@ static constexpr DecoderListEntry DecoderList32[]{
{DecoderTableXqci32, XqciFeatureGroup, "Qualcomm uC Extensions"},
{DecoderTableXRivos32, XRivosFeatureGroup, "Rivos"},
{DecoderTable32, {}, "standard 32-bit instructions"},
- {DecoderTableRV32Only32, {}, "RV32-only standard instructions"},
+ {DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"},
{DecoderTableZfinx32, {}, "Zfinx (Float in Integer)"},
{DecoderTableZdinxRV32Only32, {}, "RV32-only Zdinx (Double in Integer)"},
};
@@ -734,8 +734,8 @@ static constexpr DecoderListEntry DecoderList16[]{
// Standard Extensions
// DecoderTableZicfiss16 must be checked before DecoderTable16.
{DecoderTableZicfiss16, {}, "Zicfiss (Shadow Stack 16-bit)"},
- {DecoderTable16, {}, "standard 16-bit Instructions"},
- {DecoderTableRV32Only16, {}, "RV32-only 16-bit Instructions"},
+ {DecoderTable16, {}, "standard 16-bit instructions"},
+ {DecoderTableRV32Only16, {}, "RV32-only 16-bit instructions"},
// Zc* instructions incompatible with Zcf or Zcd
{DecoderTableZcOverlap16,
{},
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