[llvm] [AMDGPU] Add SchedGroupBarrier::PACK for packed math (PR #132432)

[Jeffrey Byrnes via llvm-commits]

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@@ -1347,6 +1347,7 @@ The AMDGPU backend implements the following LLVM IR intrinsics.
                                                    - 0x0100: All DS read instructions may be scheduled accoss sched_barrier.
                                                    - 0x0200: All DS write instructions may be scheduled across sched_barrier.
                                                    - 0x0400: All Transcendental (e.g. V_EXP) instructions may be scheduled across sched_barrier.
+                                                   - 0x0800: All Packed Arithmetic (e.g. V_PK_MOV, V_DOT, etc) instructions may be scheduled across sched_barrier.
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jrbyrnes wrote:

> All of these should be in terms of hardware defined scheduling resource

Well, that is sort of the intention here. There are a subset of VALU instructions that have distinct hardware based scheduling concerns as they cannot be coissued / coexecuted on certain architectures. The alternative approach was to offer a sched.group for non-coissue instructions, but we thought this was too narrow and architecture dependent -- thus I decided to use VOP3P as a proxy. Do you prefer the more specific approach?

https://github.com/llvm/llvm-project/pull/132432