[llvm] [MCA] Extend -instruction-tables option with verbosity levels (PR #130574)

[Julien Villette via llvm-commits]

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@@ -141,6 +241,33 @@ void InstructionInfoView::collectData(
     IIVDEntry.mayLoad = MCDesc.mayLoad();
     IIVDEntry.mayStore = MCDesc.mayStore();
     IIVDEntry.hasUnmodeledSideEffects = MCDesc.hasUnmodeledSideEffects();
+
+    if (PrintFullInfo) {
+      // Get latency with bypass
+      IIVDEntry.Bypass =
+          IIVDEntry.Latency - MCSchedModel::getBypassDelayCycles(STI, SCDesc);
+      IIVDEntry.OpcodeName = MCII.getName(Inst.getOpcode());
+      raw_string_ostream TempStream(IIVDEntry.Resources);
+      const MCWriteProcResEntry *Index = STI.getWriteProcResBegin(&SCDesc);
+      const MCWriteProcResEntry *Last = STI.getWriteProcResEnd(&SCDesc);
+      auto Sep = "";
+      for (; Index != Last; ++Index) {
+        if (!Index->ReleaseAtCycle)
+          continue;
+        const MCProcResourceDesc *MCProc =
+            SM.getProcResource(Index->ProcResourceIdx);
+        if (Index->ReleaseAtCycle > 1) {
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jvillette38 wrote:

In practice, do you have `AcquireAtCycle` not defined to 0 for at least one resource?
I think it has no sense to define `AcquireAtCycle` != 0 on all resources. So, throughput depends only on `ReleaseAtCycle`.
Example `vlm.v`: `SiFive7VCQ,SiFive7VL[1,3]`. First resource has `AcquireAtCycle` == 0 and `ReleaseAtCycle` == 1.
Are you agree with that?

https://github.com/llvm/llvm-project/pull/130574