[llvm] [ConstraintElimination] Add additional facts for bitwise AND OR (PR #132124)

[Lee Wei via llvm-commits]

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@@ -1605,6 +1605,30 @@ void ConstraintInfo::addFact(CmpInst::Predicate Pred, Value *A, Value *B,
                              unsigned NumIn, unsigned NumOut,
                              SmallVectorImpl<StackEntry> &DFSInStack) {
   addFactImpl(Pred, A, B, NumIn, NumOut, DFSInStack, false);
+
+  Value *LHS;
+  Value *RHS;
+  if (match(A, m_Or(m_Value(LHS), m_Value(RHS)))) {
+    // (LHS | RHS >= 0) =>  LHS >= 0 && RHS >= 0
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leewei05 wrote:

@dtcxzyw I wanted to handle as many patterns as possible. Also, constraint elimination adds certain facts with ICMP_SGE and I want to make sure that those facts can be handled as well. Even if X <=/>= 0 are not canonical forms, can these patterns exist after running InstCombine?

Btw, is there a documentation for these canonical forms? Or these canonical forms can only be found in InstCombine code.

https://github.com/llvm/llvm-project/pull/132124