[llvm] [RISCV] Support VP_SPLAT mask operations (PR #132345)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff 75ab43b70eef125dbdf1586143fad88a2a61170e 051d1c03fdca0625640939229f90b4cdc345a33c --extensions cpp -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 133906ba6d..1ee189e8bb 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -12786,9 +12786,9 @@ SDValue RISCVTargetLowering::lowerVPSplatExperimental(SDValue Op,
             DAG.getNode(RISCVISD::VMAND_VL, DL, ContainerVT, Result, Mask, VL);
     } else {
       MVT WidenVT = ContainerVT.changeVectorElementType(MVT::i8);
-      SDValue LHS = DAG.getNode(
-          RISCVISD::VMV_V_X_VL, DL, WidenVT, DAG.getUNDEF(WidenVT),
-          DAG.getZExtOrTrunc(Val, DL, Subtarget.getXLenVT()), VL);
+      SDValue LHS =
+          DAG.getNode(RISCVISD::VMV_V_X_VL, DL, WidenVT, DAG.getUNDEF(WidenVT),
+                      DAG.getZExtOrTrunc(Val, DL, Subtarget.getXLenVT()), VL);
       SDValue RHS = DAG.getConstant(0, DL, WidenVT);
       Result = DAG.getNode(RISCVISD::SETCC_VL, DL, ContainerVT,
                            {LHS, RHS, DAG.getCondCode(ISD::SETNE),

``````````

</details>


https://github.com/llvm/llvm-project/pull/132345