[llvm] [DAG][X86]added shrd in combineor for bzhiq+shlq+or (PR #125734)

[Simon Pilgrim via llvm-commits]

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@@ -0,0 +1,90 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefixes=X64,X64-FAST
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+slow-shld | FileCheck %s --check-prefixes=X64,X64-SLOW
+
+define  i64 @updateTop10Bits_64bits(i64  %A, i64  %B) {
+; X64-FAST-LABEL: updateTop10Bits_64bits:
+; X64-FAST:         # %bb.0:
+; X64-FAST-NEXT:    movq	%rdi, %rax
+; X64-FAST-NEXT:    shlq	$10, %rax
+; X64-FAST-NEXT:    shrdq	$10, %rsi, %rax
+; X64-FAST-NEXT:    retq
+;
+; X64-SLOW-LABEL: updateTop10Bits_64bits:
+; X64-SLOW:         # %bb.0:
+; X64-SLOW-NEXT:    movabsq $18014398509481983, %rax
+; X64-SLOW-NEXT:    andq    %rdi, %rax
+; X64-SLOW-NEXT:    shlq    $54, %rsi
+; X64-SLOW-NEXT:    orq     %rsi, %rax
+; X64-SLOW-NEXT:    retq
+entry:
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RKSimon wrote:

remove `entry:` lines

https://github.com/llvm/llvm-project/pull/125734