[llvm] [SystemZ, DebugInfo] Support InstrRef-based Debug Value Tracking in the SystemZ backend (PR #132415)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 21 09:08:24 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-systemz
Author: Dominik Steenken (dominik-steenken)
<details>
<summary>Changes</summary>
This PR follows the guide published [here](https://github.com/llvm/llvm-project/blob/main/llvm/docs/InstrRefDebugInfo.md#required-target-support-and-transition-guide) in order to support instr-ref-based debug value tracking on SystemZ. It is broadly divided into two parts:
### Implementing required backend functions
Commits e032f69 and 18bcb09 implement the backend functions
- `SystemZInstrInfo::isCopyInstrImpl`
- `SystemZInstrInfo::isLoadFromStackSlotPostFE`
- `SystemZInstrInfo::isStoreToStackSlotPostFE`
In order to support the `LiveDebugValues` pass in properly tracking values through memory and registers. This had an unexpected side effect in the `AsmPrinter`. Detection of folded vs. non-folded stack spills and reloads now functions properly, and so a number of tests that were expecting "wrong" annotations from the `AsmPrinter` had to be modified.
### Instrumenting the Backend Passes
The remaining commits go through the optimization passes implemented in the SystemZ backend and instrument them with calls to `MachineFunction::substituteDebugValuesForInst` where appropriate. Some details are available in the individual commit messages, but a few points are worth addressing directly:
- The `systemz-ld-cleanup` pass does not require instrumentation, even though it replaces `TLS_LDCALL` instructions with `COPY` instructions. This is because, while `TLS_LDCALL` is capable of carrying a `debug-instr-number`, it would never actually have one in the real world, as even an explicit reference to the address of a thread-local global variable would be resolved into a series of instructions culminating in an add that would end up carrying the `debug-instr-number` instead of the `TLS_LDCALL`.
- The `systemz-copy-physregs` pass was not initialized like the other backend passes, which led to it no being addressable via `llc --run-pass=<passname>` for, e.g., `.mir` testcases. This is fixed in this PR as well
- The substitutions added in this PR are inserted where "regular" registers, i.e. GPRs, FPRs, or VRs, are the target of instructions that get replaced by new instructions. I specifically did not consider the effect on the `cc` register, as i believed that we wouldn't be tracking values through that register. However, `MachineFunction::substituteDebugValuesForInst` by default seems to record substitutions for `def cc` as well, as can, e.g., be seen at `llvm/test/CodeGen/SystemZ/Large/debug-instrref-brct.py:6`, where a substitution arises from replacing a branch-on-count instruction, which has an `implicit-def` of `cc` (which in this case is not technically real, but the larger question remains).
- There are many instances where backend passes mutate potentially tracked instructions rather than replace them. These always seemed to be cases where the value tracked did not change, and also still resided in the same operand, so i did not instrument these instruction mutations. However, the above doc link suggests to drop the debug instr number whenever a mutation takes place. I'm unsure whether that applies in this case, so some guidance would be appreciated.
---
Patch is 165.88 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/132415.diff
28 Files Affected:
- (modified) llvm/lib/Target/SystemZ/SystemZCopyPhysRegs.cpp (+5-1)
- (modified) llvm/lib/Target/SystemZ/SystemZElimCompare.cpp (+9)
- (modified) llvm/lib/Target/SystemZ/SystemZInstrFP.td (+8-6)
- (modified) llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp (+54)
- (modified) llvm/lib/Target/SystemZ/SystemZInstrInfo.h (+7)
- (modified) llvm/lib/Target/SystemZ/SystemZInstrInfo.td (+4-2)
- (modified) llvm/lib/Target/SystemZ/SystemZInstrVector.td (+5-3)
- (modified) llvm/lib/Target/SystemZ/SystemZLongBranch.cpp (+9-4)
- (modified) llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp (+22-11)
- (modified) llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp (+1)
- (added) llvm/test/CodeGen/SystemZ/Large/debug-instrref-brct.py (+33)
- (modified) llvm/test/CodeGen/SystemZ/builtin-setjmp-alloca.ll (+32-32)
- (modified) llvm/test/CodeGen/SystemZ/builtin-setjmp-spills.ll (+56-56)
- (modified) llvm/test/CodeGen/SystemZ/builtin-setjmp.ll (+32-32)
- (added) llvm/test/CodeGen/SystemZ/debug-instrref-copyphysregs.mir (+22)
- (added) llvm/test/CodeGen/SystemZ/debug-instrref-elimcompare.mir (+65)
- (added) llvm/test/CodeGen/SystemZ/debug-instrref-postrewrite.mir (+24)
- (modified) llvm/test/CodeGen/SystemZ/fmuladd-soft-float.ll (+7-7)
- (modified) llvm/test/CodeGen/SystemZ/foldmemop-imm-02.mir (+2-2)
- (modified) llvm/test/CodeGen/SystemZ/foldmemop-vec-cc.mir (+1-1)
- (modified) llvm/test/CodeGen/SystemZ/foldmemop-vec-cmp.mir (+4-4)
- (modified) llvm/test/CodeGen/SystemZ/foldmemop-vec-unary.mir (+4-4)
- (modified) llvm/test/CodeGen/SystemZ/fp-move-02.ll (+51-51)
- (modified) llvm/test/CodeGen/SystemZ/frame-22.ll (+10-10)
- (modified) llvm/test/CodeGen/SystemZ/int-uadd-03.ll (+2-2)
- (modified) llvm/test/CodeGen/SystemZ/int-usub-03.ll (+2-2)
- (modified) llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll (+426-426)
- (modified) llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll (+16-16)
``````````diff
diff --git a/llvm/lib/Target/SystemZ/SystemZCopyPhysRegs.cpp b/llvm/lib/Target/SystemZ/SystemZCopyPhysRegs.cpp
index 8979ce4386607..a6cf0f57aaf06 100644
--- a/llvm/lib/Target/SystemZ/SystemZCopyPhysRegs.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZCopyPhysRegs.cpp
@@ -75,6 +75,7 @@ bool SystemZCopyPhysRegs::visitMBB(MachineBasicBlock &MBB) {
DebugLoc DL = MI->getDebugLoc();
Register SrcReg = MI->getOperand(1).getReg();
Register DstReg = MI->getOperand(0).getReg();
+
if (DstReg.isVirtual() &&
(SrcReg == SystemZ::CC || SystemZ::AR32BitRegClass.contains(SrcReg))) {
Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass);
@@ -89,7 +90,10 @@ bool SystemZCopyPhysRegs::visitMBB(MachineBasicBlock &MBB) {
SystemZ::AR32BitRegClass.contains(DstReg)) {
Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass);
MI->getOperand(0).setReg(Tmp);
- BuildMI(MBB, MBBI, DL, TII->get(SystemZ::SAR), DstReg).addReg(Tmp);
+ MachineInstr *NMI =
+ BuildMI(MBB, MBBI, DL, TII->get(SystemZ::SAR), DstReg).addReg(Tmp);
+ // SAR now writes the final value to DstReg, so update debug values.
+ MBB.getParent()->substituteDebugValuesForInst(*MI, *NMI);
Modified = true;
}
}
diff --git a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
index 9f4d4aaa68fa3..789365fb9e311 100644
--- a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
@@ -227,6 +227,9 @@ bool SystemZElimCompare::convertToBRCT(
// this is not necessary there.
if (BRCT != SystemZ::BRCTH)
MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);
+ // The debug instr tracking for the counter now used by BRCT needs to be
+ // updated.
+ MI.getParent()->getParent()->substituteDebugValuesForInst(MI, *MIB);
MI.eraseFromParent();
return true;
}
@@ -268,6 +271,9 @@ bool SystemZElimCompare::convertToLoadAndTrap(
.add(MI.getOperand(1))
.add(MI.getOperand(2))
.add(MI.getOperand(3));
+ // The debug instr tracking for the load target now used by the load-and-trap
+ // needs to be updated.
+ MI.getParent()->getParent()->substituteDebugValuesForInst(MI, *Branch);
MI.eraseFromParent();
return true;
}
@@ -288,6 +294,9 @@ bool SystemZElimCompare::convertToLoadAndTest(
for (const auto &MO : MI.operands())
MIB.add(MO);
MIB.setMemRefs(MI.memoperands());
+ // The debug instr tracking for the load target now needs to be updated
+ // because the load has moved to a new instruction
+ MI.getParent()->getParent()->substituteDebugValuesForInst(MI, *MIB);
MI.eraseFromParent();
// Mark instruction as not raising an FP exception if applicable. We already
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFP.td b/llvm/lib/Target/SystemZ/SystemZInstrFP.td
index c171982b45692..bef38b9cb809b 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFP.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFP.td
@@ -42,13 +42,15 @@ let isAsCheapAsAMove = 1, isMoveImm = 1 in {
}
// Moves between two floating-point registers.
-def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>;
-def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>;
-def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>;
+let isMoveReg = 1 in {
+ def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>;
+ def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>;
+ def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>;
+ // For z13 we prefer LDR over LER to avoid partial register dependencies.
+ let isCodeGenOnly = 1 in
+ def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>;
+}
-// For z13 we prefer LDR over LER to avoid partial register dependencies.
-let isCodeGenOnly = 1 in
- def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>;
// Moves between two floating-point registers that also set the condition
// codes. Note that these instructions will turn SNaNs into QNaNs and should
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index ab2e5b3c9a190..5c1f3709612dd 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -346,6 +346,52 @@ Register SystemZInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
}
+Register SystemZInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const {
+ // if this is not a simple load from memory, it's not a load from stack slot
+ // either.
+ const MCInstrDesc &MCID = MI.getDesc();
+ if (!(MCID.TSFlags & SystemZII::SimpleBDXLoad))
+ return 0;
+
+ Register Reg;
+ // If the frame index is still there, use it.
+ if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
+ return Reg;
+ SmallVector<const MachineMemOperand *, 1> Accesses;
+ // Otherwise, attempt to derive frame index from MachineMemOperands
+ if (hasLoadFromStackSlot(MI, Accesses)) {
+ FrameIndex =
+ cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
+ ->getFrameIndex();
+ return MI.getOperand(0).getReg();
+ }
+ return 0;
+}
+
+Register SystemZInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const {
+ // if this is not a simple store to memory, it's not a store to stack slot
+ // either.
+ const MCInstrDesc &MCID = MI.getDesc();
+ if (!(MCID.TSFlags & SystemZII::SimpleBDXStore))
+ return 0;
+
+ Register Reg;
+ // If the frame index is still there, use it.
+ if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
+ return Reg;
+ // Otherwise, attempt to derive frame index from MachineMemOperands
+ SmallVector<const MachineMemOperand *, 1> Accesses;
+ if (hasStoreToStackSlot(MI, Accesses)) {
+ FrameIndex =
+ cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
+ ->getFrameIndex();
+ return MI.getOperand(0).getReg();
+ }
+ return 0;
+}
+
bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr &MI,
int &DestFrameIndex,
int &SrcFrameIndex) const {
@@ -2316,3 +2362,11 @@ bool SystemZInstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
return false;
}
+
+std::optional<DestSourcePair>
+SystemZInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
+ // if MI is a simple single-register copy operation, return operand pair
+ if (MI.isMoveReg())
+ return DestSourcePair(MI.getOperand(0), MI.getOperand(1));
+ return std::nullopt;
+}
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
index 5f09ad508905d..a8d282dd9e417 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
@@ -232,6 +232,10 @@ class SystemZInstrInfo : public SystemZGenInstrInfo {
int &FrameIndex) const override;
Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
+ Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const override;
+ Register isStoreToStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const override;
bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
int &SrcFrameIndex) const override;
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
@@ -386,6 +390,9 @@ class SystemZInstrInfo : public SystemZGenInstrInfo {
bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg,
int64_t &ImmVal) const override;
+
+ std::optional<DestSourcePair>
+ isCopyInstrImpl(const MachineInstr &MI) const override;
};
} // end namespace llvm
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 2acb4b0339d32..4f75e0132610e 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -424,8 +424,10 @@ defm CondStore64 : CondStores<GR64, simple_store,
//===----------------------------------------------------------------------===//
// Register moves.
-def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>;
-def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>;
+let isMoveReg = 1 in {
+ def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>;
+ def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>;
+}
let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>;
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrVector.td b/llvm/lib/Target/SystemZ/SystemZInstrVector.td
index 3187d91b00046..7043850d9eca5 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrVector.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrVector.td
@@ -12,9 +12,11 @@
let Predicates = [FeatureVector] in {
// Register move.
- def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>;
- def VLR32 : UnaryAliasVRR<null_frag, v32sb, v32sb>;
- def VLR64 : UnaryAliasVRR<null_frag, v64db, v64db>;
+ let isMoveReg = 1 in {
+ def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>;
+ def VLR32 : UnaryAliasVRR<null_frag, v32sb, v32sb>;
+ def VLR64 : UnaryAliasVRR<null_frag, v64db, v64db>;
+ }
// Load GR from VR element.
def VLGV : BinaryVRScGeneric<"vlgv", 0xE721>;
diff --git a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
index 36d76235398ed..f19b932f3c731 100644
--- a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
@@ -374,16 +374,19 @@ void SystemZLongBranch::splitBranchOnCount(MachineInstr *MI,
unsigned AddOpcode) {
MachineBasicBlock *MBB = MI->getParent();
DebugLoc DL = MI->getDebugLoc();
- BuildMI(*MBB, MI, DL, TII->get(AddOpcode))
- .add(MI->getOperand(0))
- .add(MI->getOperand(1))
- .addImm(-1);
+ MachineInstr *AddImm = BuildMI(*MBB, MI, DL, TII->get(AddOpcode))
+ .add(MI->getOperand(0))
+ .add(MI->getOperand(1))
+ .addImm(-1);
MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL))
.addImm(SystemZ::CCMASK_ICMP)
.addImm(SystemZ::CCMASK_CMP_NE)
.add(MI->getOperand(2));
// The implicit use of CC is a killing use.
BRCL->addRegisterKilled(SystemZ::CC, &TII->getRegisterInfo());
+ // The result of the BRANCH ON COUNT MI is the new count in register 0, so the
+ // debug tracking needs to go to the result of the Add immediate.
+ MBB->getParent()->substituteDebugValuesForInst(*MI, *AddImm);
MI->eraseFromParent();
}
@@ -402,6 +405,8 @@ void SystemZLongBranch::splitCompareBranch(MachineInstr *MI,
.add(MI->getOperand(3));
// The implicit use of CC is a killing use.
BRCL->addRegisterKilled(SystemZ::CC, &TII->getRegisterInfo());
+ // Since we are replacing branches that did not compute any value, no debug
+ // value substitution is necessary.
MI->eraseFromParent();
}
diff --git a/llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp b/llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp
index 4b16bcf95d51c..ffeba87795625 100644
--- a/llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp
@@ -19,6 +19,7 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
using namespace llvm;
@@ -108,15 +109,19 @@ void SystemZPostRewrite::selectSELRMux(MachineBasicBlock &MBB,
bool DestIsHigh = SystemZ::isHighReg(DestReg);
bool Src1IsHigh = SystemZ::isHighReg(Src1Reg);
bool Src2IsHigh = SystemZ::isHighReg(Src2Reg);
+ // A copy instruction that we might create, held here for the purpose of
+ // debug instr value tracking.
+ MachineInstr *CopyInst = nullptr;
// In rare cases both sources are the same register (after
// machine-cse). This must be handled as it may lead to wrong-code (after
// machine-cp) if the kill flag on Src1 isn't cleared (with
// expandCondMove()).
if (Src1Reg == Src2Reg) {
- BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(),
- TII->get(SystemZ::COPY), DestReg)
- .addReg(Src1Reg, getRegState(Src1MO) & getRegState(Src2MO));
+ CopyInst = BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(),
+ TII->get(SystemZ::COPY), DestReg)
+ .addReg(Src1Reg, getRegState(Src1MO) & getRegState(Src2MO));
+ MBB.getParent()->substituteDebugValuesForInst(*MBBI, *CopyInst, 1);
MBBI->eraseFromParent();
return;
}
@@ -126,21 +131,24 @@ void SystemZPostRewrite::selectSELRMux(MachineBasicBlock &MBB,
// first. But only if this doesn't clobber the other source.
if (DestReg != Src1Reg && DestReg != Src2Reg) {
if (DestIsHigh != Src1IsHigh) {
- BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(),
- TII->get(SystemZ::COPY), DestReg)
- .addReg(Src1Reg, getRegState(Src1MO));
+ CopyInst = BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(),
+ TII->get(SystemZ::COPY), DestReg)
+ .addReg(Src1Reg, getRegState(Src1MO));
Src1MO.setReg(DestReg);
Src1Reg = DestReg;
Src1IsHigh = DestIsHigh;
} else if (DestIsHigh != Src2IsHigh) {
- BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(),
- TII->get(SystemZ::COPY), DestReg)
- .addReg(Src2Reg, getRegState(Src2MO));
+ CopyInst = BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(),
+ TII->get(SystemZ::COPY), DestReg)
+ .addReg(Src2Reg, getRegState(Src2MO));
Src2MO.setReg(DestReg);
Src2Reg = DestReg;
Src2IsHigh = DestIsHigh;
}
}
+ // if a copy instruction was inserted, record the debug value substitution
+ if (CopyInst)
+ MBB.getParent()->substituteDebugValuesForInst(*MBBI, *CopyInst, 1);
// If the destination (now) matches one source, prefer this to be first.
if (DestReg != Src1Reg && DestReg == Src2Reg) {
@@ -204,8 +212,11 @@ bool SystemZPostRewrite::expandCondMove(MachineBasicBlock &MBB,
// In MoveMBB, emit an instruction to move SrcReg into DestReg,
// then fall through to RestMBB.
- BuildMI(*MoveMBB, MoveMBB->end(), DL, TII->get(SystemZ::COPY), DestReg)
- .addReg(MI.getOperand(2).getReg(), getRegState(MI.getOperand(2)));
+ MachineInstr *CopyInst =
+ BuildMI(*MoveMBB, MoveMBB->end(), DL, TII->get(SystemZ::COPY), DestReg)
+ .addReg(MI.getOperand(2).getReg(), getRegState(MI.getOperand(2)));
+ // record the debug value substitution for CopyInst
+ MBB.getParent()->substituteDebugValuesForInst(*MBBI, *CopyInst, 1);
MoveMBB->addSuccessor(RestMBB);
NextMBBI = MBB.end();
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
index 092515ee197a8..6300fb72990d0 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
@@ -48,6 +48,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTarget() {
initializeSystemZPostRewritePass(PR);
initializeSystemZTDCPassPass(PR);
initializeSystemZDAGToDAGISelLegacyPass(PR);
+ initializeSystemZCopyPhysRegsPass(PR);
}
static std::string computeDataLayout(const Triple &TT) {
diff --git a/llvm/test/CodeGen/SystemZ/Large/debug-instrref-brct.py b/llvm/test/CodeGen/SystemZ/Large/debug-instrref-brct.py
new file mode 100644
index 0000000000000..05593a672bf05
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/Large/debug-instrref-brct.py
@@ -0,0 +1,33 @@
+# RUN: %python %s | llc -mtriple=s390x-linux-gnu -x mir --run-pass=systemz-long-branch \
+# RUN: | FileCheck %s
+
+# CHECK: debugValueSubstitutions:
+# CHECK: - { srcinst: 1, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 }
+# CHECK: - { srcinst: 1, srcop: 3, dstinst: 3, dstop: 3, subreg: 0 }
+# CHECK-NEXT: constants: []
+# CHECK: $r3l = AHI $r3l, -1
+# CHECK-NEXT: BRCL 14, 6, %bb.2
+print(" name: main")
+print(" alignment: 16")
+print(" tracksRegLiveness: true")
+print(" liveins: ")
+print(" - { reg: '$r1d', virtual-reg: '' }")
+print(" - { reg: '$r2d', virtual-reg: '' }")
+print(" - { reg: '$r3l', virtual-reg: '' }")
+print(" - { reg: '$r4l', virtual-reg: '' }")
+print(" debugValueSubstitutions: []")
+print(" body: |")
+print(" bb.0:")
+print(" liveins: $r3l, $r4l, $r2d, $r3d")
+print(" $r3l = BRCT $r3l, %bb.2, implicit-def $cc, debug-instr-number 1")
+print(" J %bb.1, debug-instr-number 2")
+print(" bb.1:")
+print(" liveins: $r1d, $r2d")
+for i in range(0, 8192):
+ print(" $r1d = LGR $r2d")
+ print(" $r2d = LGR $r1d")
+print(" Return implicit $r2d")
+print(" bb.2:")
+print(" liveins: $r4l")
+print(" Return implicit $r4l")
+
diff --git a/llvm/test/CodeGen/SystemZ/builtin-setjmp-alloca.ll b/llvm/test/CodeGen/SystemZ/builtin-setjmp-alloca.ll
index f714599f9a8f2..9bd6ff8eea4c5 100644
--- a/llvm/test/CodeGen/SystemZ/builtin-setjmp-alloca.ll
+++ b/llvm/test/CodeGen/SystemZ/builtin-setjmp-alloca.ll
@@ -30,14 +30,14 @@ define signext i32 @foo() "frame-pointer"="all" {
; CHECK-NEXT: .cfi_def_cfa_offset 400
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
-; CHECK-NEXT: std %f8, 232(%r11) # 8-byte Folded Spill
-; CHECK-NEXT: std %f9, 224(%r11) # 8-byte Folded Spill
-; CHECK-NEXT: std %f10, 216(%r11) # 8-byte Folded Spill
-; CHECK-NEXT: std %f11, 208(%r11) # 8-byte Folded Spill
-; CHECK-NEXT: std %f12, 200(%r11) # 8-byte Folded Spill
-; CHECK-NEXT: std %f13, 192(%r11) # 8-byte Folded Spill
-; CHECK-NEXT: std %f14, 184(%r11) # 8-byte Folded Spill
-; CHECK-NEXT: std %f15, 176(%r11) # 8-byte Folded Spill
+; CHECK-NEXT: std %f8, 232(%r11) # 8-byte Spill
+; CHECK-NEXT: std %f9, 224(%r11) # 8-byte Spill
+; CHECK-NEXT: std %f10, 216(%r11) # 8-byte Spill
+; CHECK-NEXT: std %f11, 208(%r11) # 8-byte Spill
+; CHECK-NEXT: std %f12, 200(%r11) # 8-byte Spill
+; CHECK-NEXT: std %f13, 192(%r11) # 8-byte Spill
+; CHECK-NEXT: std %f14, 184(%r11) # 8-byte Spill
+; CHECK-NEXT: std %f15, 176(%r11) # 8-byte Spill
; CHECK-NEXT: .cfi_offset %f8, -168
; CHECK-NEXT: .cfi_offset %f9, -176
; CHECK-NEXT: .cfi_offset %f10, -184
@@ -59,14 +59,14 @@ define signext i32 @foo() "frame-pointer"="all" {
; CHECK-NEXT: .LBB0_2: # %entry
; CHECK-NEXT: lg %r1, 168(%r11)
; CHECK-NEXT: lgf %r2, 0(%r1)
-; CHECK-NEXT: ld %f8, 232(%r11) # 8-byte Folded Reload
-; CHECK-NEXT: ld %f9, 224(%r11) # 8-byte Folded Reload
-; CHECK-NEXT: ld %f10, 216(%r11) # 8-byte Folded Reload
-; CHECK-NEXT: ld %f11, 208(%r11) # 8-byte Folded Reload
-; CHECK-NEXT: ld %f12, 200(%r11) # 8-byte Folded Reload
-; CHECK-NEXT: ld %f13, 192(%r11) # 8-byte Folded Reload
-; CHECK-NEXT: ld %f14, 184(%r11) # 8-byte Folded Reload
-; CHECK-NEXT: ld %f15, 176(%r11) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f8, 232(%r11) # 8-byte Reload
+; CHECK-NEXT: ld %f9, 224(%r11) # 8-byte Reload
+; CHECK-NEXT: ld %f10, 216(%r11) # 8-byte Reload
+; CHECK-NEXT: ld %f11, 208(%r11) # 8-byte Reload
+; CHECK-NEXT: ld %f12, 200(%r11) # 8-byte Reload
+; CHECK-NEXT: ld %f13, 192(%r11) # 8-byte Reload
+; CHECK-NEXT: ld %f14, 184(%r11) # 8-byte Reload
+; CHECK-NEXT: ld %f15, 176(%r11) # 8-byte Reload
; CHECK-NEXT: lmg %r6, %r15, 288(%r11)
; CHECK-NEXT: br %r14
entry:
@@ -101,14 +101,14 @@ define signext i32 @foo1() "backchain" "frame-pointer"="all" {
; CHECK-NEXT: stg %r1, 0(%r15)
; CHECK-NEXT: lgr %r11, %r15
; CHECK-NEXT: .cfi_def_cfa_register %r11
-; CHECK-NEXT: std %f8, 232(%r11) # 8-byte Folded Spill
-; CHECK-NEXT: std %f9, 224(%r11) # 8-byte Folded Spill
-; CHECK-NEXT: std %f10, 216(%r11) # 8-byte Folded Spill
-; CHECK-NEXT: ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/132415
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