[llvm] 415dd38 - [RISCV][MC] Correct the register state update for auipc (#130897)

[via llvm-commits]

Author: liulin92
Date: 2025-03-19T16:50:55+08:00
New Revision: 415dd383e4066717178870f1927f542a3d96621a

URL: https://github.com/llvm/llvm-project/commit/415dd383e4066717178870f1927f542a3d96621a
DIFF: https://github.com/llvm/llvm-project/commit/415dd383e4066717178870f1927f542a3d96621a.diff

LOG: [RISCV][MC] Correct the register state update for auipc (#130897)

AUIPC is a 20-bits value which is used to form 32-bits offset thus it
should be a int32 value, then signed-extend to int64.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
    llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 5f1d7b03f3218..d1bc6aa9a1e33 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -195,7 +195,7 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
     }
     case RISCV::AUIPC:
       setGPRState(Inst.getOperand(0).getReg(),
-                  Addr + (Inst.getOperand(1).getImm() << 12));
+                  Addr + SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
       break;
     }
   }

diff  --git a/llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s b/llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s
index 2be42ad1c1164..a2525394a0bf5 100644
--- a/llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s
+++ b/llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s
@@ -78,3 +78,9 @@ nop
 bar:
 # CHECK: 60: c.nop
 nop
+
+# CHECK-LABEL: 00011000 <far>:
+.org 0x11000
+far:
+# CHECK: jalr ra, 0x0(ra) <foo>
+call foo