[clang] [llvm] [RISCV] Add Qualcomm uC Xqcilb (Long Branch) extension (PR #131996)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 19 03:14:05 PDT 2025
https://github.com/hchandel created https://github.com/llvm/llvm-project/pull/131996
This extension adds two long branch instructions.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0
This patch adds assembler only support.
Co-authored-by: Sudharsan Veeravalli <quic_svs at quicinc.com>
>From e3f9548f1ccdf1bb85d0c540c7bdea6094019278 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <quic_hchandel at quicinc.com>
Date: Mon, 17 Mar 2025 17:29:09 +0530
Subject: [PATCH 1/4] [RISCV] Add Qualcomm uC Xqcilb (Long Branch) extension
This extension adds two long branch instructions.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0
This patch adds assembler only support.
Change-Id: I262d59edc8c7266800badc82d6496619ce2aeabf
---
.../Driver/print-supported-extensions-riscv.c | 1 +
llvm/docs/RISCVUsage.rst | 3 ++
llvm/docs/ReleaseNotes.md | 2 +
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 16 ++++++++
.../RISCV/Disassembler/RISCVDisassembler.cpp | 6 +--
llvm/lib/Target/RISCV/RISCVFeatures.td | 8 ++++
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 40 +++++++++++++++++++
llvm/lib/TargetParser/RISCVISAInfo.cpp | 6 +--
llvm/test/CodeGen/RISCV/attributes.ll | 2 +
llvm/test/MC/RISCV/xqcilb-invalid.s | 24 +++++++++++
llvm/test/MC/RISCV/xqcilb-valid.s | 26 ++++++++++++
.../TargetParser/RISCVISAInfoTest.cpp | 3 +-
12 files changed, 130 insertions(+), 7 deletions(-)
create mode 100644 llvm/test/MC/RISCV/xqcilb-invalid.s
create mode 100644 llvm/test/MC/RISCV/xqcilb-valid.s
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 912a3ad4b6d6e..12337912a6695 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -202,6 +202,7 @@
// CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension)
// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension)
// CHECK-NEXT: xqciint 0.4 'Xqciint' (Qualcomm uC Interrupts Extension)
+// CHECK-NEXT: xqcilb 0.2 'Xqcilb' (Qualcomm uC Long Branch Extension)
// CHECK-NEXT: xqcili 0.2 'Xqcili' (Qualcomm uC Load Large Immediate Extension)
// CHECK-NEXT: xqcilia 0.2 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 32a65d898bb31..9ce78a6673bfe 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -456,6 +456,9 @@ The current vendor extensions supported are:
``experimental-Xqciint``
LLVM implements `version 0.4 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
+``experimental-Xqcilb``
+ LLVM implements `version 0.2 of the Qualcomm uC Long Branch extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
+
``experimental-Xqcili``
LLVM implements `version 0.2 of the Qualcomm uC Load Large Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index eb050e2747bc5..b4f2c7f792bd2 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -110,6 +110,8 @@ Changes to the PowerPC Backend
Changes to the RISC-V Backend
-----------------------------
+* Adds experimental assembler support for the Qualcomm uC 'Xqcilb` (Long Branch)
+ extension.
* Adds experimental assembler support for the Qualcomm uC 'Xqcili` (Load Large Immediate)
extension.
* Adds experimental assembler support for the Qualcomm uC 'Xqcilia` (Large Immediate Arithmetic)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 7c5f1fc08cd0b..6163b27a35d3b 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1106,6 +1106,17 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_RISCV_None;
}
+ bool isSImm32Lsb0() const {
+ if (!isImm())
+ return false;
+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+ int64_t Imm;
+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+ return IsConstantImm &&
+ isShiftedInt<31, 1>(fixImmediateForRV32(Imm, isRV64Imm())) &&
+ VK == RISCVMCExpr::VK_RISCV_None;
+ }
+
/// getStartLoc - Gets location of the first token of this operand
SMLoc getStartLoc() const override { return StartLoc; }
/// getEndLoc - Gets location of the last token of this operand
@@ -1729,6 +1740,11 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return generateImmOutOfRangeError(Operands, ErrorInfo,
std::numeric_limits<int32_t>::min(),
std::numeric_limits<uint32_t>::max());
+ case Match_InvalidSImm32Lsb0:
+ return generateImmOutOfRangeError(
+ Operands, ErrorInfo, std::numeric_limits<int32_t>::min(),
+ std::numeric_limits<int32_t>::max() - 1,
+ "operand must be a multiple of 2 bytes in the range ");
case Match_InvalidRnumArg: {
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 10);
}
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index f979af4cbe999..33b8b4ed9de21 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -651,9 +651,9 @@ static constexpr FeatureBitset XqciFeatureGroup = {
RISCV::FeatureVendorXqcibm, RISCV::FeatureVendorXqcicli,
RISCV::FeatureVendorXqcicm, RISCV::FeatureVendorXqcics,
RISCV::FeatureVendorXqcicsr, RISCV::FeatureVendorXqciint,
- RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilia,
- RISCV::FeatureVendorXqcilo, RISCV::FeatureVendorXqcilsm,
- RISCV::FeatureVendorXqcisls,
+ RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilb,
+ RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo,
+ RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisls,
};
static constexpr FeatureBitset XSfVectorGroup = {
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 1480d700fbc81..096b196045341 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1359,6 +1359,14 @@ def HasVendorXqciint
AssemblerPredicate<(all_of FeatureVendorXqciint),
"'Xqciint' (Qualcomm uC Interrupts Extension)">;
+def FeatureVendorXqcilb
+ : RISCVExperimentalExtension<0, 2, "Qualcomm uC Long Branch Extension",
+ [FeatureStdExtZca]>;
+
+def HasVendorXqcilb : Predicate<"Subtarget->hasVendorXqcilb()">,
+ AssemblerPredicate<(all_of FeatureVendorXqcilb),
+ "'Xqcilb' (Qualcomm uC oad Large Immediate Extension)">;
+
def FeatureVendorXqcili
: RISCVExperimentalExtension<0, 2, "Qualcomm uC Load Large Immediate Extension",
[FeatureStdExtZca]>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index a8e642d04fd3a..1fdf61b3d0e07 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -75,6 +75,21 @@ def simm32 : RISCVOp<XLenVT> {
}];
}
+// A 32-bit signed immediate where the least significant bit is zero.
+def simm32_lsb0 : Operand<OtherVT> {
+ let ParserMatchClass = SImmAsmOperand<32, "Lsb0">;
+ let PrintMethod = "printBranchOperand";
+ let EncoderMethod = "getImmOpValueAsr1";
+ let DecoderMethod = "decodeSImmOperandAndLsl1<32>";
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ return isShiftedInt<31, 1>(Imm);
+ }];
+ let OperandType = "OPERAND_PCREL";
+}
+
//===----------------------------------------------------------------------===//
// Instruction Formats
//===----------------------------------------------------------------------===//
@@ -345,6 +360,24 @@ class QCIRVInstEI<bits<3> funct3, bits<2> funct2, string opcodestr>
(ins GPRNoX0:$rs1, simm26:$imm), opcodestr,
"$rd, $rs1, $imm">;
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class QCIRVInst48EJ<bits<2> func2, string opcodestr>
+ : RVInst48<(outs), (ins simm32_lsb0:$imm31),
+ opcodestr, "$imm31", [], InstFormatQCEJ> {
+ bits<31> imm31;
+
+ let Inst{47-32} = imm31{30-15};
+ let Inst{31} = imm31{11};
+ let Inst{30-25} = imm31{9-4};
+ let Inst{24-20} = 0b00000;
+ let Inst{19-17} = imm31{14-12};
+ let Inst{16-15} = func2;
+ let Inst{14-12} = 0b100;
+ let Inst{11-8} = imm31{3-0};
+ let Inst{7} = imm31{10};
+ let Inst{6-0} = 0b0011111;
+}
+
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
@@ -593,6 +626,13 @@ let Predicates = [HasVendorXqcilo, IsRV32] in {
def QC_E_SW : QCIRVInstESStore<0b110, 0b11, "qc.e.sw">;
} // Predicates = [HasVendorXqcilo, IsRV32]
+let Predicates = [HasVendorXqcilb, IsRV32] in {
+ let isCall = 1, Defs = [X1] in
+ def QC_E_JAL : QCIRVInst48EJ<0b01, "qc.e.jal">;
+ let isBranch = 1, isTerminator = 1, isBarrier = 1 in
+ def QC_E_J : QCIRVInst48EJ<0b00, "qc.e.j">;
+} // Predicates = [HasVendorXqcilb, IsRV32]
+
let Predicates = [HasVendorXqcili, IsRV32] in {
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
def QC_LI : RVInstU<OPC_OP_IMM_32, (outs GPRNoX0:$rd), (ins simm20:$imm20),
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index ecd397f451c79..736bbf3161607 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -744,9 +744,9 @@ Error RISCVISAInfo::checkDependency() {
bool HasXqccmp = Exts.count("xqccmp") != 0;
static constexpr StringLiteral XqciExts[] = {
- {"xqcia"}, {"xqciac"}, {"xqcibm"}, {"xqcicli"}, {"xqcicm"},
- {"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqcili"}, {"xqcilia"},
- {"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
+ {"xqcia"}, {"xqciac"}, {"xqcibm"}, {"xqcicli"}, {"xqcicm"},
+ {"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqcilb"}, {"xqcili"},
+ {"xqcilia"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
static constexpr StringLiteral ZcdOverlaps[] = {
{"zcmt"}, {"zcmp"}, {"xqccmp"}, {"xqciac"}, {"xqcicm"}};
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 659de283a1a7e..0745bb8789e59 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -90,6 +90,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics %s -o - | FileCheck --check-prefix=RV32XQCICS %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciint %s -o - | FileCheck --check-prefix=RV32XQCIINT %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilb %s -o - | FileCheck --check-prefix=RV32XQCILB %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcili %s -o - | FileCheck --check-prefix=RV32XQCILI %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilia %s -o - | FileCheck --check-prefix=RV32XQCILIA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilo %s -o - | FileCheck --check-prefix=RV32XQCILO %s
@@ -413,6 +414,7 @@
; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2"
; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2"
; RV32XQCIINT: .attribute 5, "rv32i2p1_zca1p0_xqciint0p4"
+; RV32XQCILB: .attribute 5, "rv32i2p1_zca1p0_xqcilb0p2"
; RV32XQCILI: .attribute 5, "rv32i2p1_zca1p0_xqcili0p2"
; RV32XQCILIA: .attribute 5, "rv32i2p1_zca1p0_xqcilia0p2"
; RV32XQCILO: .attribute 5, "rv32i2p1_zca1p0_xqcilo0p2"
diff --git a/llvm/test/MC/RISCV/xqcilb-invalid.s b/llvm/test/MC/RISCV/xqcilb-invalid.s
new file mode 100644
index 0000000000000..1a9009b26b691
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqcilb-invalid.s
@@ -0,0 +1,24 @@
+# Xqcilb - Qualcomm uC Long Branch Extension
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcilb < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s
+# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcilb < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.j
+
+# CHECK-PLUS: :[[@LINE+1]]:9: error: operand must be a multiple of 2 bytes in the range [-2147483648, 2147483646]
+qc.e.j -2147483649
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilb' (Qualcomm uC Long Branch Extension)
+qc.e.j -2147483648
+
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.jal
+
+# CHECK-PLUS: :[[@LINE+1]]:10: error: operand must be a multiple of 2 bytes in the range [-2147483648, 2147483646]
+qc.e.jal 2147483649
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilb' (Qualcomm uC Long Branch Extension)
+qc.e.jal 2147483640
diff --git a/llvm/test/MC/RISCV/xqcilb-valid.s b/llvm/test/MC/RISCV/xqcilb-valid.s
new file mode 100644
index 0000000000000..1c722e3b3173e
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqcilb-valid.s
@@ -0,0 +1,26 @@
+# Xqcilb - Qualcomm uC Long Branch Extension
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilb -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilb < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xqcilb -M no-aliases --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefix=CHECK-OBJ %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilb -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilb < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xqcilb --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefix=CHECK-OBJ %s
+
+# CHECK-INST: qc.e.j -2147483648
+# CHECK-OBJ: qc.e.j 0x80000000
+# CHECK-ENC: encoding: [0x1f,0x40,0x00,0x00,0x00,0x80]
+qc.e.j -2147483648
+
+# CHECK-INST: qc.e.jal 2147483640
+# CHECK-OBJ: qc.e.jal 0x7ffffffe
+# CHECK-ENC: encoding: [0x9f,0xcc,0x0e,0xfe,0xff,0x7f]
+qc.e.jal 2147483640
+
+# CHECK-INST: qc.e.jal -116
+# CHECK-OBJ: qc.e.jal 0xffffff98
+# CHECK-ENC: encoding: [0x9f,0xc6,0x0e,0xf8,0xff,0xff]
+qc.e.jal 0xffffff8c
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 40a74cef2e3f3..76ba4bc47ad06 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -658,7 +658,7 @@ TEST(ParseArchString, RejectsConflictingExtensions) {
"rv64i_xqcicsr0p2", "rv64i_xqcilsm0p2", "rv64i_xqcicm0p2",
"rv64i_xqcics0p2", "rv64i_xqcicli0p2", "rv64i_xqciint0p4",
"rv64i_xqcilo0p2", "rv64i_xqcili0p2", "rv64i_xqcilia0p2",
- "rv64i_xqcibm0p4"}) {
+ "rv64i_xqcibm0p4", "rv64i_xqcilb0p2"}) {
EXPECT_THAT(
toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
::testing::EndsWith(" is only supported for 'rv32'"));
@@ -1142,6 +1142,7 @@ Experimental extensions
xqcics 0.2
xqcicsr 0.2
xqciint 0.4
+ xqcilb 0.2
xqcili 0.2
xqcilia 0.2
xqcilo 0.2
>From be5ad34ea475a78c614dfa872989698c4864a07a Mon Sep 17 00:00:00 2001
From: Harsh Chandel <quic_hchandel at quicinc.com>
Date: Mon, 17 Mar 2025 17:38:55 +0530
Subject: [PATCH 2/4] fixup! Minor change
Change-Id: I0afb1b8f8ab442a83477e09917634db0b3ac6093
---
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 1fdf61b3d0e07..2c69aec7951dc 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -363,7 +363,7 @@ class QCIRVInstEI<bits<3> funct3, bits<2> funct2, string opcodestr>
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class QCIRVInst48EJ<bits<2> func2, string opcodestr>
: RVInst48<(outs), (ins simm32_lsb0:$imm31),
- opcodestr, "$imm31", [], InstFormatQCEJ> {
+ opcodestr, "$imm31", [], InstFormatOther> {
bits<31> imm31;
let Inst{47-32} = imm31{30-15};
>From 9db5c773b4891c9a795025ec408e08b381cd28ad Mon Sep 17 00:00:00 2001
From: Harsh Chandel <quic_hchandel at quicinc.com>
Date: Tue, 18 Mar 2025 11:37:50 +0530
Subject: [PATCH 3/4] fixup! Update RISCVFeatures.td
Change-Id: I969bb0f122a467c8b36308f6ce016d9f7e53a88b
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 096b196045341..76323b5191809 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1365,7 +1365,7 @@ def FeatureVendorXqcilb
def HasVendorXqcilb : Predicate<"Subtarget->hasVendorXqcilb()">,
AssemblerPredicate<(all_of FeatureVendorXqcilb),
- "'Xqcilb' (Qualcomm uC oad Large Immediate Extension)">;
+ "'Xqcilb' (Qualcomm uC Long Branch Extension)">;
def FeatureVendorXqcili
: RISCVExperimentalExtension<0, 2, "Qualcomm uC Load Large Immediate Extension",
>From 34963ca036b7c35068b9cd135945d36d9076de34 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <quic_hchandel at quicinc.com>
Date: Wed, 19 Mar 2025 15:40:53 +0530
Subject: [PATCH 4/4] fixup! Clang format
Change-Id: I15118e0e3b96c380e44e07c6c344ec8ac20e2eeb
---
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 8 ++++----
llvm/lib/TargetParser/RISCVISAInfo.cpp | 7 ++++---
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 651ddfde74c89..d5ca56c7e46e3 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -651,10 +651,10 @@ static constexpr FeatureBitset XqciFeatureGroup = {
RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm,
RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm,
RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,
- RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqcilb, RISCV::FeatureVendorXqcili,
- RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo,
- RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisim,
- RISCV::FeatureVendorXqcisls,
+ RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqcilb,
+ RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilia,
+ RISCV::FeatureVendorXqcilo, RISCV::FeatureVendorXqcilsm,
+ RISCV::FeatureVendorXqcisim, RISCV::FeatureVendorXqcisls,
};
static constexpr FeatureBitset XSfVectorGroup = {
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index b11e0155b5133..8ebae8f70a652 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -744,9 +744,10 @@ Error RISCVISAInfo::checkDependency() {
bool HasXqccmp = Exts.count("xqccmp") != 0;
static constexpr StringLiteral XqciExts[] = {
- {"xqcia"}, {"xqciac"}, {"xqcibi"}, {"xqcibm"}, {"xqcicli"},
- {"xqcicm"}, {"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqcilb"}, {"xqcili"},
- {"xqcilia"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisim"}, {"xqcisls"}};
+ {"xqcia"}, {"xqciac"}, {"xqcibi"}, {"xqcibm"},
+ {"xqcicli"}, {"xqcicm"}, {"xqcics"}, {"xqcicsr"},
+ {"xqciint"}, {"xqcilb"}, {"xqcili"}, {"xqcilia"},
+ {"xqcilo"}, {"xqcilsm"}, {"xqcisim"}, {"xqcisls"}};
static constexpr StringLiteral ZcdOverlaps[] = {
{"zcmt"}, {"zcmp"}, {"xqccmp"}, {"xqciac"}, {"xqcicm"}};
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