[llvm] d2c41fb - [RISCV] Correct the predicates for the flh/fsh InstAlias and assembler pseudos to include Zfbfmin. (#131920)

via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 18 17:55:40 PDT 2025 

Author: Craig Topper
Date: 2025-03-18T17:55:36-07:00
New Revision: d2c41fb85d960e094a16686fb0ff67d9a2f01d8d

URL: https://github.com/llvm/llvm-project/commit/d2c41fb85d960e094a16686fb0ff67d9a2f01d8d
DIFF: https://github.com/llvm/llvm-project/commit/d2c41fb85d960e094a16686fb0ff67d9a2f01d8d.diff

LOG: [RISCV] Correct the predicates for the flh/fsh InstAlias and assembler pseudos to include Zfbfmin. (#131920)

Added: 
    llvm/test/MC/RISCV/rvzfbfmin-aliases-valid.s
    llvm/test/MC/RISCV/rvzfhmin-aliases-valid.s

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    llvm/test/MC/RISCV/rv32i-invalid.s
    llvm/test/MC/RISCV/rvzfh-pseudos.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
index ea0b814ac7ba5..48b7ca516a820 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -218,7 +218,7 @@ foreach Ext = ZfhminDExts in {
 // Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasStdExtZfhmin] in {
+let Predicates = [HasHalfFPLoadStoreMove] in {
 def : InstAlias<"flh $rd, (${rs1})",  (FLH FPR16:$rd,  GPR:$rs1, 0), 0>;
 def : InstAlias<"fsh $rs2, (${rs1})", (FSH FPR16:$rs2, GPR:$rs1, 0), 0>;
 } // Predicates = [HasStdExtZfhmin]
@@ -241,7 +241,7 @@ def PseudoQuietFLT_H : PseudoQuietFCMP<FPR16>;
 }
 } // Predicates = [HasStdExtZfh]
 
-let Predicates = [HasStdExtZfhmin] in {
+let Predicates = [HasHalfFPLoadStoreMove] in {
 def PseudoFLH  : PseudoFloatLoad<"flh", FPR16>;
 def PseudoFSH  : PseudoStore<"fsh", FPR16>;
 } // Predicates = [HasStdExtZfhmin]

diff  --git a/llvm/test/MC/RISCV/rv32i-invalid.s b/llvm/test/MC/RISCV/rv32i-invalid.s
index 1ffb10789bbbd..31b074103fb2c 100644
--- a/llvm/test/MC/RISCV/rv32i-invalid.s
+++ b/llvm/test/MC/RISCV/rv32i-invalid.s
@@ -190,7 +190,7 @@ fadd.h ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the foll
 fadd.s a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfinx' (Float in Integer){{$}}
 fadd.d a0, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer){{$}}
 fadd.h a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer){{$}}
-flh ft0, (a0) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}}
+flh ft0, (a0) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
 sh1add a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zba' (Address Generation Instructions) or 'Base P' (Packed-SIMD){{$}}
 clz a0, a1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation) or 'Base P' (Packed-SIMD){{$}}
 clmul a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbc' (Carry-Less Multiplication) or 'Zbkc' (Carry-less multiply instructions for Cryptography){{$}}

diff  --git a/llvm/test/MC/RISCV/rvzfbfmin-aliases-valid.s b/llvm/test/MC/RISCV/rvzfbfmin-aliases-valid.s
new file mode 100644
index 0000000000000..79704c14cc874
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvzfbfmin-aliases-valid.s
@@ -0,0 +1,31 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfbfmin -M no-aliases \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfbfmin \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfbfmin -M no-aliases \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfbfmin \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zfbfmin < %s \
+# RUN:     | llvm-objdump -d --mattr=+zfbfmin --no-print-imm-hex -M no-aliases - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zfbfmin < %s \
+# RUN:     | llvm-objdump -d --mattr=+zfbfmin --no-print-imm-hex - \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zfbfmin < %s \
+# RUN:     | llvm-objdump -d --mattr=+zfbfmin --no-print-imm-hex -M no-aliases - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zfbfmin < %s \
+# RUN:     | llvm-objdump -d --mattr=+zfbfmin --no-print-imm-hex - \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===----------------------------------------------------------------------===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===----------------------------------------------------------------------===##
+
+# CHECK-INST: flh ft0, 0(a0)
+# CHECK-ALIAS: flh ft0, 0(a0)
+flh f0, (x10)
+# CHECK-INST: fsh ft0, 0(a0)
+# CHECK-ALIAS: fsh ft0, 0(a0)
+fsh f0, (x10)

diff  --git a/llvm/test/MC/RISCV/rvzfh-pseudos.s b/llvm/test/MC/RISCV/rvzfh-pseudos.s
index e1ba0a55dd606..09074e1a80c3c 100644
--- a/llvm/test/MC/RISCV/rvzfh-pseudos.s
+++ b/llvm/test/MC/RISCV/rvzfh-pseudos.s
@@ -1,5 +1,7 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfh | FileCheck %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfh | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfhmin | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfhmin | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfbfmin | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfbfmin | FileCheck %s
 
 # CHECK: .Lpcrel_hi0:
 # CHECK: auipc a2, %pcrel_hi(a_symbol)

diff  --git a/llvm/test/MC/RISCV/rvzfhmin-aliases-valid.s b/llvm/test/MC/RISCV/rvzfhmin-aliases-valid.s
new file mode 100644
index 0000000000000..a0672c1c07fe3
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvzfhmin-aliases-valid.s
@@ -0,0 +1,31 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfhmin -M no-aliases \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfhmin \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfhmin -M no-aliases \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfhmin \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zfhmin < %s \
+# RUN:     | llvm-objdump -d --mattr=+zfhmin --no-print-imm-hex -M no-aliases - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zfhmin < %s \
+# RUN:     | llvm-objdump -d --mattr=+zfhmin --no-print-imm-hex - \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zfhmin < %s \
+# RUN:     | llvm-objdump -d --mattr=+zfhmin --no-print-imm-hex -M no-aliases - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zfhmin < %s \
+# RUN:     | llvm-objdump -d --mattr=+zfhmin --no-print-imm-hex - \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===----------------------------------------------------------------------===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===----------------------------------------------------------------------===##
+
+# CHECK-INST: flh ft0, 0(a0)
+# CHECK-ALIAS: flh ft0, 0(a0)
+flh f0, (x10)
+# CHECK-INST: fsh ft0, 0(a0)
+# CHECK-ALIAS: fsh ft0, 0(a0)
+fsh f0, (x10)

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