[llvm] 467e5a1 - [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (#128833)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 18 09:05:27 PDT 2025
Author: Sudharsan Veeravalli
Date: 2025-03-18T09:05:22-07:00
New Revision: 467e5a1d41d63fd1c80fee14a8d99d32515c26d6
URL: https://github.com/llvm/llvm-project/commit/467e5a1d41d63fd1c80fee14a8d99d32515c26d6
DIFF: https://github.com/llvm/llvm-project/commit/467e5a1d41d63fd1c80fee14a8d99d32515c26d6.diff
LOG: [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (#128833)
This extension adds 10 instructions that provide hints to the interface
simulation environment.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/
This patch adds assembler only support.
Added:
llvm/test/MC/RISCV/xqcisim-invalid.s
llvm/test/MC/RISCV/xqcisim-valid.s
Modified:
clang/test/Driver/print-supported-extensions-riscv.c
llvm/docs/RISCVUsage.rst
llvm/docs/ReleaseNotes.md
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
llvm/lib/TargetParser/RISCVISAInfo.cpp
llvm/test/CodeGen/RISCV/attributes.ll
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Removed:
################################################################################
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index f3388b9335b76..019106abfabc3 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -207,6 +207,7 @@
// CHECK-NEXT: xqcilia 0.2 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
+// CHECK-NEXT: xqcisim 0.2 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
// CHECK-NEXT: xrivosvisni 0.1 'XRivosVisni' (Rivos Vector Integer Small New)
// CHECK-NEXT: xrivosvizip 0.1 'XRivosVizip' (Rivos Vector Register Zips)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 98bce186e3ee5..cf7be8b2c5c96 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -471,6 +471,9 @@ The current vendor extensions supported are:
``experimental-Xqcilsm``
LLVM implements `version 0.2 of the Qualcomm uC Load Store Multiple extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
+``experimental-Xqcisim``
+ LLVM implements `version 0.2 of the Qualcomm uC Simulation Hint extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
+
``experimental-Xqcisls``
LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 0d3c4d98f86fe..b191a840d9803 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -126,6 +126,8 @@ Changes to the RISC-V Backend
'Xqccmp' extension, which is a frame-pointer convention compatible version of
Zcmp.
* Added non-quadratic ``log-vrgather`` cost model for ``vrgather.vv`` instruction
+* Adds experimental assembler support for the Qualcomm uC 'Xqcisim` (Simulation Hint)
+ extension.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index a5d410193cc43..e3c4cc36ee822 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -653,7 +653,8 @@ static constexpr FeatureBitset XqciFeatureGroup = {
RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,
RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqcili,
RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo,
- RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisls,
+ RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisim,
+ RISCV::FeatureVendorXqcisls,
};
static constexpr FeatureBitset XSfVectorGroup = {
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 3757cdbe384dc..74224b2e150e4 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1407,6 +1407,14 @@ def HasVendorXqccmp : Predicate<"Subtarget->hasVendorXqccmp()">,
AssemblerPredicate<(all_of FeatureVendorXqccmp),
"'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)">;
+def FeatureVendorXqcisim
+ : RISCVExperimentalExtension<0, 2, "Qualcomm uC Simulation Hint Extension",
+ [FeatureStdExtZca]>;
+def HasVendorXqcisim
+ : Predicate<"Subtarget->hasVendorXqcisim()">,
+ AssemblerPredicate<(all_of FeatureVendorXqcisim),
+ "'Xqcisim' (Qualcomm uC Simulation Hint Extension)">;
+
// Rivos Extension(s)
def FeatureVendorXRivosVisni
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 921a2ff8afa96..59fd13c6d683a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -336,6 +336,19 @@ class QCIInt_IMM<bits<1> funct1, string opcodestr>
let Inst{24-20} = imm10{9-5};
}
+class QCISim_NONE<bits<4> imm11_8, string opcodestr>
+ : RVInstI<0b010, OPC_OP_IMM, (outs), (ins), opcodestr, ""> {
+ let rs1 = 0;
+ let rd = 0;
+ let imm12 = {imm11_8, 0b00000000};
+}
+
+class QCISim_RS1<bits<4> imm11_8, string opcodestr>
+ : RVInstI<0b010, OPC_OP_IMM, (outs), (ins GPR:$rs1), opcodestr, "$rs1"> {
+ let rd = 0;
+ let imm12 = {imm11_8, 0b00000000};
+}
+
class QCIRVInstEIBase<bits<3> funct3, bits<2> funct2, dag outs,
dag ins, string opcodestr, string argstr>
: RVInst48<outs, ins, opcodestr, argstr, [], InstFormatOther> {
@@ -691,6 +704,41 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
} // Predicates = [HasVendorXqcilia, IsRV32]
+let Predicates = [HasVendorXqcisim, IsRV32] in {
+let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
+ def QC_PSYSCALLI : RVInstI<0b010, OPC_OP_IMM, (outs), (ins uimm10:$imm10),
+ "qc.psyscalli", "$imm10"> {
+ bits<10> imm10;
+
+ let rs1 = 0;
+ let rd = 0;
+ let imm12 = {0b00, imm10};
+ }
+
+ def QC_PPUTCI : RVInstI<0b010, OPC_OP_IMM, (outs), (ins uimm8:$imm8),
+ "qc.pputci", "$imm8"> {
+ bits<8> imm8;
+
+ let rs1 = 0;
+ let rd = 0;
+ let imm12 = {0b0100, imm8};
+ }
+
+ def QC_PCOREDUMP : QCISim_NONE<0b0110, "qc.pcoredump">;
+ def QC_PPREGS : QCISim_NONE<0b0111, "qc.ppregs">;
+ def QC_PPREG : QCISim_RS1<0b1000, "qc.ppreg">;
+ def QC_PPUTC : QCISim_RS1<0b1001, "qc.pputc">;
+ def QC_PPUTS : QCISim_RS1<0b1010, "qc.pputs">;
+ def QC_PEXIT : QCISim_RS1<0b1011, "qc.pexit">;
+ def QC_PSYSCALL : QCISim_RS1<0b1100, "qc.psyscall">;
+
+ def QC_C_PTRACE : RVInst16CI<0b000, 0b10, (outs), (ins), "qc.c.ptrace", ""> {
+ let rd = 0;
+ let imm = 0;
+ }
+} // mayLoad = 0, mayStore = 0, hasSideEffects = 1
+} // Predicates = [HasVendorXqcisim, IsRV32]
+
} // DecoderNamespace = "Xqci"
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 41bbff8195e38..d10c334330a14 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -746,7 +746,7 @@ Error RISCVISAInfo::checkDependency() {
static constexpr StringLiteral XqciExts[] = {
{"xqcia"}, {"xqciac"}, {"xqcibi"}, {"xqcibm"}, {"xqcicli"},
{"xqcicm"}, {"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqcili"},
- {"xqcilia"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
+ {"xqcilia"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisim"}, {"xqcisls"}};
static constexpr StringLiteral ZcdOverlaps[] = {
{"zcmt"}, {"zcmp"}, {"xqccmp"}, {"xqciac"}, {"xqcicm"}};
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 02f43516b58e2..a5cbc7f0cf882 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -95,6 +95,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilia %s -o - | FileCheck --check-prefix=RV32XQCILIA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilo %s -o - | FileCheck --check-prefix=RV32XQCILO %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilsm %s -o - | FileCheck --check-prefix=RV32XQCILSM %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisim %s -o - | FileCheck --check-prefix=RV32XQCISIM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s
; RUN: llc -mtriple=riscv32 -mattr=+zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s
; RUN: llc -mtriple=riscv32 -mattr=+zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s
@@ -419,6 +420,7 @@
; RV32XQCILIA: .attribute 5, "rv32i2p1_zca1p0_xqcilia0p2"
; RV32XQCILO: .attribute 5, "rv32i2p1_zca1p0_xqcilo0p2"
; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2"
+; RV32XQCISIM: attribute 5, "rv32i2p1_zca1p0_xqcisim0p2"
; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2"
; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo1p0"
; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc1p0"
diff --git a/llvm/test/MC/RISCV/xqcisim-invalid.s b/llvm/test/MC/RISCV/xqcisim-invalid.s
new file mode 100644
index 0000000000000..c8fe925b623f6
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqcisim-invalid.s
@@ -0,0 +1,125 @@
+# Xqcisim - Simulaton Hint Instructions
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcisim < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s
+# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcisim < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s
+
+# CHECK-PLUS: :[[@LINE+1]]:14: error: immediate must be an integer in the range [0, 1023]
+qc.psyscalli 1024
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.psyscalli
+
+# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction
+qc.psyscalli 23, x0
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
+qc.psyscalli 1023
+
+
+# CHECK-PLUS: :[[@LINE+1]]:11: error: immediate must be an integer in the range [0, 255]
+qc.pputci 256
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.pputci
+
+# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
+qc.pputci 200, x8
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
+qc.pputci 255
+
+
+# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
+qc.c.ptrace x0
+
+# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
+qc.c.ptrace 1
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
+qc.c.ptrace
+
+
+# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction
+qc.pcoredump 12
+
+# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction
+qc.pcoredump x4
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
+qc.pcoredump
+
+
+# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction
+qc.ppregs x1
+
+# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction
+qc.ppregs 23
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
+qc.ppregs
+
+
+# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction
+qc.ppreg x10, x2
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.ppreg
+
+# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction
+qc.ppreg 23
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
+qc.ppreg a0
+
+
+# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction
+qc.pputc x7, x3
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.pputc
+
+# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction
+qc.pputc 34
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
+qc.pputc t2
+
+
+# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction
+qc.pputs x15, x18
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.pputs
+
+# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction
+qc.pputs 45
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
+qc.pputs a5
+
+
+# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction
+qc.pexit x26, x23
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.pexit
+
+# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction
+qc.pexit 78
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
+qc.pexit s10
+
+
+# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction
+qc.psyscall x11, x5
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.psyscall
+
+# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
+qc.psyscall 98
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
+qc.psyscall a1
diff --git a/llvm/test/MC/RISCV/xqcisim-valid.s b/llvm/test/MC/RISCV/xqcisim-valid.s
new file mode 100644
index 0000000000000..668f279643c74
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqcisim-valid.s
@@ -0,0 +1,52 @@
+# Xqcisim - Simulation Hint Instructions
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisim -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisim < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xqcisim -M no-aliases --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisim -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisim < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xqcisim --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+
+
+# CHECK-INST: qc.psyscalli 1023
+# CHECK-ENC: encoding: [0x13,0x20,0xf0,0x3f]
+qc.psyscalli 1023
+
+# CHECK-INST: qc.pputci 255
+# CHECK-ENC: encoding: [0x13,0x20,0xf0,0x4f]
+qc.pputci 255
+
+# CHECK-INST: qc.c.ptrace
+# CHECK-ENC: encoding: [0x02,0x00]
+qc.c.ptrace
+
+# CHECK-INST: qc.pcoredump
+# CHECK-ENC: encoding: [0x13,0x20,0x00,0x60]
+qc.pcoredump
+
+# CHECK-INST: qc.ppregs
+# CHECK-ENC: encoding: [0x13,0x20,0x00,0x70]
+qc.ppregs
+
+# CHECK-INST: qc.ppreg a0
+# CHECK-ENC: encoding: [0x13,0x20,0x05,0x80]
+qc.ppreg x10
+
+# CHECK-INST: qc.pputc t2
+# CHECK-ENC: encoding: [0x13,0xa0,0x03,0x90]
+qc.pputc x7
+
+# CHECK-INST: qc.pputs a5
+# CHECK-ENC: encoding: [0x13,0xa0,0x07,0xa0]
+qc.pputs x15
+
+# CHECK-INST: qc.pexit s10
+# CHECK-ENC: encoding: [0x13,0x20,0x0d,0xb0]
+qc.pexit x26
+
+# CHECK-INST: qc.psyscall a1
+# CHECK-ENC: encoding: [0x13,0xa0,0x05,0xc0]
+qc.psyscall x11
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 9efb863e311c6..04082a89124ee 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -658,7 +658,7 @@ TEST(ParseArchString, RejectsConflictingExtensions) {
"rv64i_xqcicsr0p2", "rv64i_xqcilsm0p2", "rv64i_xqcicm0p2",
"rv64i_xqcics0p2", "rv64i_xqcicli0p2", "rv64i_xqciint0p4",
"rv64i_xqcilo0p2", "rv64i_xqcilia0p2", "rv64i_xqcibm0p4",
- "rv64i_xqcibi0p2", "rv64i_xqcili0p2"}) {
+ "rv64i_xqcibi0p2", "rv64i_xqcili0p2", "rv64i_xqcisim0p2"}) {
EXPECT_THAT(
toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
::testing::EndsWith(" is only supported for 'rv32'"));
@@ -1147,6 +1147,7 @@ Experimental extensions
xqcilia 0.2
xqcilo 0.2
xqcilsm 0.2
+ xqcisim 0.2
xqcisls 0.2
xrivosvisni 0.1
xrivosvizip 0.1
More information about the llvm-commits
mailing list