[llvm] [AMDGCN] Allow unscheduling of bundled insns (PR #129769)

[Julian Brown via llvm-commits]

https://github.com/jtb20 updated https://github.com/llvm/llvm-project/pull/129769

>From b1dc02017d4d9ba89d4574521681a43b9e3eae21 Mon Sep 17 00:00:00 2001
From: Julian Brown <julian.brown at amd.com>
Date: Tue, 4 Mar 2025 10:34:11 -0600
Subject: [PATCH] [AMDGCN] Allow unscheduling of bundled insns

This is a patch arising from AMD's fuzzing project.

In the test case, the scheduling algorithm decides to undo an attempted
schedule, but is unprepared to handle bundled instructions at that
point -- and those can arise via the expansion of intrinsics earlier
in compilation.  The fix is to use the splice method instead of
remove/insert, since that can handle bundles properly.
---
 llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp    |  3 +--
 .../CodeGen/AMDGPU/sema-v-unsched-bundle.ll    | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/sema-v-unsched-bundle.ll

diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index c277223de13ac..5dcf523430fd2 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -1567,8 +1567,7 @@ void GCNSchedStage::revertScheduling() {
     }
 
     if (MI->getIterator() != DAG.RegionEnd) {
-      DAG.BB->remove(MI);
-      DAG.BB->insert(DAG.RegionEnd, MI);
+      DAG.BB->splice(DAG.RegionEnd, DAG.BB, MI);
       if (!MI->isDebugInstr())
         DAG.LIS->handleMove(*MI, true);
     }
diff --git a/llvm/test/CodeGen/AMDGPU/sema-v-unsched-bundle.ll b/llvm/test/CodeGen/AMDGPU/sema-v-unsched-bundle.ll
new file mode 100644
index 0000000000000..febfab649dded
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/sema-v-unsched-bundle.ll
@@ -0,0 +1,18 @@
+; REQUIRES: asserts
+; RUN: llc -mtriple=amdgcn -O1 -mcpu=gfx90a -debug-only=machine-scheduler -filetype=null < %s 2>&1 | FileCheck --check-prefix=DEBUG %s
+
+; DEBUG: Attempting to revert scheduling.
+
+ at G = global <32 x i8> splat (i8 1)
+ at G.1 = global <32 x i8> splat (i8 127)
+
+define amdgpu_kernel void @gws_sema_v_offset0(i32 %val, <32 x i1>* %inp) #0 {
+  %LGV1 = load <32 x i8>, ptr @G.1, align 32
+  %LGV = load <32 x i8>, ptr @G, align 32
+  call void @llvm.amdgcn.ds.gws.sema.v(i32 0)
+  %C = icmp ne <32 x i8> %LGV, %LGV1
+  store <32 x i1> %C, ptr %inp, align 4
+  ret void
+}
+
+declare void @llvm.amdgcn.ds.gws.sema.v(i32) #1