[llvm] [ARM]Adjust cost of muls in SMLAL patterns (PR #122713)

[Nashe Mncube via llvm-commits]

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@@ -1458,16 +1458,76 @@ InstructionCost ARMTTIImpl::getArithmeticInstrCost(
   if (LooksLikeAFreeShift())
     return 0;
 
+  // When targets have both DSP and MVE we find that the
+  // the compiler will attempt to vectorize as well as using
+  // scalar (S/U)MLAL operations. This is in cases where we have
+  // the pattern ext(mul(ext(i16), ext(i16))) we find
+  // that generated codegen performs better when only using (S/U)MLAL scalar
+  // ops instead of trying to mix vector ops with (S/U)MLAL ops. We therefore
+  // check if a mul instruction is used in a SMLAL pattern.
+  auto MulInDSPMLALPattern = [&](const Instruction *I, unsigned Opcode,
+                                 Type *Ty) -> bool {
+    if (!ST->hasDSP())
+      return false;
+
+    if (!I)
+      return false;
+
+    if (Opcode != Instruction::Mul)
+      return false;
+
+    if (Ty->isVectorTy())
+      return false;
+
+    auto IsSExtInst = [](const Value *V) -> bool { return isa<SExtInst>(V); };
+    auto IsZExtInst = [](const Value *V) -> bool { return isa<ZExtInst>(V); };
+    auto IsExtInst = [&, IsSExtInst, IsZExtInst](const Value *V) -> bool {
+      return IsSExtInst(V) || IsZExtInst(V);
+    };
+    auto IsExtensionFromHalf = [&, IsSExtInst,
+                                IsZExtInst](const Value *V) -> bool {
+      if (IsSExtInst(V))
+        return dyn_cast<SExtInst>(V)->getOperand(0)->getType()->isIntegerTy(16);
+      if (IsZExtInst(V))
+        return dyn_cast<ZExtInst>(V)->getOperand(0)->getType()->isIntegerTy(16);
+      return false;
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nasherm wrote:

Done

https://github.com/llvm/llvm-project/pull/122713