[llvm] [X86] Prevent APX NDD compression when it creates a partial write (PR #132051)

[Daniel Zabawa via llvm-commits]

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@@ -7229,6 +7252,18 @@ void X86InstrInfo::breakPartialRegDependency(
         .addReg(Reg, RegState::Undef)
         .addReg(Reg, RegState::Undef);
     MI.addRegisterKilled(Reg, TRI, true);
+  } else if ((X86::GR16RegClass.contains(Reg) ||
+              X86::GR8RegClass.contains(Reg)) &&
+             X86II::hasNewDataDest(MI.getDesc().TSFlags)) {
+    // This case is only expected for NDD ops which appear to be partial
+    // writes, but are not due to the zeroing of the upper part. Here
+    // we add an implicit def of the superegister, which prevents
+    // CompressEVEX from converting this to a legacy form.
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daniel-zabawa wrote:

I can add verification to the tests. I don't believe it's arbitrary - an NDD op always writes to the full (physical) register, so this accurately reflects the semantics post-regalloc. The idea is to indicate in MIR that the zero-upper behavior is intentional and needed. 

https://github.com/llvm/llvm-project/pull/132051