[clang] [llvm] [RISCV] Add Qualcomm uC Xqcilb (Long Branch) extension (PR #131996)

[Craig Topper via llvm-commits]

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@@ -96,6 +96,21 @@ def simm32 : RISCVOp<XLenVT> {
   }];
 }
 
+// A 32-bit signed immediate where the least significant bit is zero.
+def simm32_lsb0 : Operand<OtherVT> {
+  let ParserMatchClass = SImmAsmOperand<32, "Lsb0">;
+  let PrintMethod = "printBranchOperand";
+  let EncoderMethod = "getImmOpValueAsr1";
+  let DecoderMethod = "decodeSImmOperandAndLsl1<32>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return isShiftedInt<31, 1>(Imm);
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topperc wrote:

Are explicit immediates useful? binutils and llvm disagree on how those are treated for the existing branches/jumps. llvm treats them as relative addresses. binutils treats them as absolute addresses.

https://github.com/llvm/llvm-project/pull/131996