[llvm] [AMDGPU] Support block load/store for CSR (PR #130013)

[Matt Arsenault via llvm-commits]

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@@ -663,6 +663,18 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
     return get(Opcode).TSFlags & SIInstrFlags::FLAT;
   }
 
+  static bool isBlockLoadStore(uint16_t Opcode) {
+    switch (Opcode) {
+    case AMDGPU::SI_BLOCK_SPILL_V1024_SAVE:
+    case AMDGPU::SI_BLOCK_SPILL_V1024_RESTORE:
+    case AMDGPU::SCRATCH_STORE_BLOCK_SADDR:
+    case AMDGPU::SCRATCH_LOAD_BLOCK_SADDR:
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arsenm wrote:

do these not support the other addressing modes? 

https://github.com/llvm/llvm-project/pull/130013