[llvm] [AArch64] Don't try to vectorize fixed point to fp narrowing conversion (PR #130665)

[David Green via llvm-commits]

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@@ -5106,6 +5106,30 @@ SDValue AArch64TargetLowering::LowerVectorINT_TO_FP(SDValue Op,
   uint64_t VTSize = VT.getFixedSizeInBits();
   uint64_t InVTSize = InVT.getFixedSizeInBits();
   if (VTSize < InVTSize) {
+    // AArch64 doesn't have a direct vector instruction to convert
+    // fixed point to floating point AND narrow it at the same time.
+    // Additional rounding when the target is f32/f64 causes subtle
+    // differences across different platforms (that do have such
+    // instructions). Conversion to f16 however is fine.
+    bool IsTargetf32Orf64 = VT.getVectorElementType() == MVT::f32 ||
+                            VT.getVectorElementType() == MVT::f64;
+    bool IsTargetf16 = false;
+    if (Op.hasOneUse() && Op->user_begin()->getOpcode() == ISD::CONCAT_VECTORS) {
+      // Some vector types are split during legalization into half, followed by
+      // concatenation, followed by rounding to the original vector type. If we
+      // end up resolving to f16 type, we shouldn't worry about rounding errors.
+      SDNode *U = *Op->user_begin();
+      if (U->hasOneUse() && U->user_begin()->getOpcode() == ISD::FP_ROUND) {
+        EVT TmpVT = U->user_begin()->getValueType(0);
+        if (TmpVT.isVector() && TmpVT.getVectorElementType() == MVT::f16)
+          IsTargetf16 = true;
+      }
+    }
+
+    if (IsTargetf32Orf64 && !IsTargetf16) {
+      return SDValue();
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davemgreen wrote:

`return DAG.UnrollVectorOp(Op.getNode());`
This should help make the unsigned converts a little smaller. It would ideally handle strict-fp too, but if that still returned SDValue() at the moment that sounds OK.

https://github.com/llvm/llvm-project/pull/130665