[llvm] [RISCV] Remove the mucounteren alternate name for CSR 0x320. (PR #132498)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/132498

This is the old name for 0x320 from privilege spec 1.9. It has different semantics than mcountinhibit that is at that address now.

It doesn't look like binutils supports this name anymore so I don't think llvm should.

>From a258b0f39cd98779fb16db91ccc02f62e3a61844 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 21 Mar 2025 18:31:04 -0700
Subject: [PATCH] [RISCV] Remove the mucounteren alternate name for CSR 0x320.

This is the old name for 0x320 from privilege spec 1.9. It has
different semantics than mcountinhibit that is at that address now.

It doesn't look like binutils supports this name anymore so I don't
think llvm should.
---
 llvm/lib/Target/RISCV/RISCVSystemOperands.td |  2 --
 llvm/test/MC/RISCV/machine-csr-names.s       | 14 --------------
 2 files changed, 16 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 5b46e7df25fc8..c03ebe585079a 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -301,8 +301,6 @@ foreach i = 3...31 in
 // Machine Counter Setup
 //===----------------------------------------------------------------------===//
 def : SysReg<"mcountinhibit", 0x320>;
-let isAltName = 1 in
-def : SysReg<"mucounteren", 0x320>;
 
 // mhpmevent3-mhpmevent31 at 0x323-0x33F.
 foreach i = 3...31 in
diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s
index ba2a79f1f6aa1..356a28b347b45 100644
--- a/llvm/test/MC/RISCV/machine-csr-names.s
+++ b/llvm/test/MC/RISCV/machine-csr-names.s
@@ -1972,20 +1972,6 @@ csrrs t1, mcountinhibit, zero
 # uimm12
 csrrs t2, 0x320, zero
 
-# mucounteren
-# name
-# CHECK-INST: csrrs t1, mcountinhibit, zero
-# CHECK-ENC:  encoding: [0x73,0x23,0x00,0x32]
-# CHECK-INST-ALIAS: csrr t1, mcountinhibit
-# uimm12
-# CHECK-INST: csrrs t2, mcountinhibit, zero
-# CHECK-ENC:  encoding: [0xf3,0x23,0x00,0x32]
-# CHECK-INST-ALIAS: csrr t2, mcountinhibit
-# name
-csrrs t1, mucounteren, zero
-# uimm12
-csrrs t2, 0x320, zero
-
 # mhpmevent3
 # name
 # CHECK-INST: csrrs t1, mhpmevent3, zero