[llvm] 6419905 - [RISCV] Correct qc.e.li instruction definition (#132380)

[via llvm-commits]

Author: Sudharsan Veeravalli
Date: 2025-03-21T17:03:27-07:00
New Revision: 6419905f53d4dbdb9d49358115ccba873f674dd4

URL: https://github.com/llvm/llvm-project/commit/6419905f53d4dbdb9d49358115ccba873f674dd4
DIFF: https://github.com/llvm/llvm-project/commit/6419905f53d4dbdb9d49358115ccba873f674dd4.diff

LOG: [RISCV] Correct qc.e.li instruction definition (#132380)

The instruction has no tied operands. It was incorrectly using
QCIRVInstEAI which has a tied operand for the destination register.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index c009bd3b24682..86d31937ab7a2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -726,7 +726,16 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
     let Inst{15-12} = imm20{18-15};
   }
 
-  def QC_E_LI : QCIRVInstEAI<0b000, 0b0, "qc.e.li">;
+  def QC_E_LI : RVInst48<(outs GPRNoX0:$rd), (ins simm32:$imm),
+                         "qc.e.li", "$rd, $imm", [], InstFormatOther> {
+    bits<5> rd;
+    bits<32> imm;
+
+    let Inst{47-16} = imm;
+    let Inst{15-12} = 0b0000;
+    let Inst{11-7} = rd;
+    let Inst{6-0} = 0b0011111;
+  }
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 } // Predicates = [HasVendorXqcili, IsRV32]