[llvm] [RISCV] Add combine for shadd family of instructions. (PR #130829)

[Stefan Pintilie via llvm-commits]

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@@ -14318,35 +14317,36 @@ static SDValue transformAddShlImm(SDNode *N, SelectionDAG &DAG,
 // or 3.
 static bool checkAddiForShift(SDValue AddI, int64_t &AddConst,
                               int64_t &ShlConst) {
+  using namespace llvm::SDPatternMatch;
   // Based on testing it seems that performance degrades if the ADDI has
   // more than 2 uses.
   if (AddI->use_size() > 2)
     return false;
 
-  auto *AddConstNode = dyn_cast<ConstantSDNode>(AddI->getOperand(1));
-  if (!AddConstNode)
-    return false;
+  APInt AddVal;
+  SDValue SHLVal;
+  sd_match(AddI, m_Add(m_Value(SHLVal), m_ConstInt(AddVal)));
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stefanp-synopsys wrote:

Yes that is correct. I have added the assert.

https://github.com/llvm/llvm-project/pull/130829