[llvm] [AArch64][SVE] Reduce MaxInterleaveFactor for A510 and A520 (PR #132246)

[David Green via llvm-commits]

davemgreen wrote:

I would expect In-order cores should like unrolling, as it enables more hiding of latency hazards. (There are always times based on the trip count of the loop or the overheads that it ends up making things worse, but I would expect at least some level of interleaving to usually be useful overall).

It looks from the example code that the addressing modes in the loops is not doing very well. They are usually calculated in LSR. Could they do better, and then get the benefit of interleaving without the cost of the inefficient addressing mode calculations?

https://github.com/llvm/llvm-project/pull/132246