[llvm] 6ada38b - [RISCV][test] Add tests for sinking NOT to be fold into ANDN/ORN/XNOR/VANDN
Piotr Fusik via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 18 08:23:52 PDT 2025
Author: Piotr Fusik
Date: 2025-03-18T16:23:09+01:00
New Revision: 6ada38b248ef80a224fd2f48841b22ae3bbf5a7b
URL: https://github.com/llvm/llvm-project/commit/6ada38b248ef80a224fd2f48841b22ae3bbf5a7b
DIFF: https://github.com/llvm/llvm-project/commit/6ada38b248ef80a224fd2f48841b22ae3bbf5a7b.diff
LOG: [RISCV][test] Add tests for sinking NOT to be fold into ANDN/ORN/XNOR/VANDN
Added:
Modified:
llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
index b6344f88cddaa..a319156f8d1b8 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
@@ -438,3 +438,255 @@ define i1 @andn_snez_i64(i64 %a, i64 %b) nounwind {
%cmpeq = icmp ne i64 %and, %b
ret i1 %cmpeq
}
+
+define i32 @and_hoisted_not_i32(i32 %x, i32 %m, i1 zeroext %cond) {
+; CHECK-LABEL: and_hoisted_not_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a2, .LBB24_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: .LBB24_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i32 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = and i32 %a, %x
+ ret i32 %masked
+
+identity:
+ ret i32 %x
+}
+
+define i32 @and_hoisted_not_i32_swapped(i32 %x, i32 %m, i1 zeroext %cond) {
+; CHECK-LABEL: and_hoisted_not_i32_swapped:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a2, .LBB25_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: .LBB25_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i32 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = and i32 %x, %a
+ ret i32 %masked
+
+identity:
+ ret i32 %x
+}
+
+define i64 @and_hoisted_not_i64(i64 %x, i64 %m, i1 zeroext %cond) {
+; CHECK-LABEL: and_hoisted_not_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a4, .LBB26_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a3, a3
+; CHECK-NEXT: not a2, a2
+; CHECK-NEXT: and a0, a2, a0
+; CHECK-NEXT: and a1, a3, a1
+; CHECK-NEXT: .LBB26_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i64 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = and i64 %a, %x
+ ret i64 %masked
+
+identity:
+ ret i64 %x
+}
+
+define i64 @and_hoisted_not_i64_swapped(i64 %x, i64 %m, i1 zeroext %cond) {
+; CHECK-LABEL: and_hoisted_not_i64_swapped:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a4, .LBB27_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a3, a3
+; CHECK-NEXT: not a2, a2
+; CHECK-NEXT: and a0, a0, a2
+; CHECK-NEXT: and a1, a1, a3
+; CHECK-NEXT: .LBB27_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i64 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = and i64 %x, %a
+ ret i64 %masked
+
+identity:
+ ret i64 %x
+}
+
+define i32 @or_hoisted_not_i32(i32 %x, i32 %m, i1 zeroext %cond) {
+; CHECK-LABEL: or_hoisted_not_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a2, .LBB28_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: .LBB28_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i32 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = or i32 %a, %x
+ ret i32 %masked
+
+identity:
+ ret i32 %x
+}
+
+define i32 @or_hoisted_not_i32_swapped(i32 %x, i32 %m, i1 zeroext %cond) {
+; CHECK-LABEL: or_hoisted_not_i32_swapped:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a2, .LBB29_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: or a0, a0, a1
+; CHECK-NEXT: .LBB29_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i32 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = or i32 %x, %a
+ ret i32 %masked
+
+identity:
+ ret i32 %x
+}
+
+define i64 @or_hoisted_not_i64(i64 %x, i64 %m, i1 zeroext %cond) {
+; CHECK-LABEL: or_hoisted_not_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a4, .LBB30_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a3, a3
+; CHECK-NEXT: not a2, a2
+; CHECK-NEXT: or a0, a2, a0
+; CHECK-NEXT: or a1, a3, a1
+; CHECK-NEXT: .LBB30_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i64 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = or i64 %a, %x
+ ret i64 %masked
+
+identity:
+ ret i64 %x
+}
+
+define i64 @or_hoisted_not_i64_swapped(i64 %x, i64 %m, i1 zeroext %cond) {
+; CHECK-LABEL: or_hoisted_not_i64_swapped:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a4, .LBB31_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a3, a3
+; CHECK-NEXT: not a2, a2
+; CHECK-NEXT: or a0, a0, a2
+; CHECK-NEXT: or a1, a1, a3
+; CHECK-NEXT: .LBB31_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i64 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = or i64 %x, %a
+ ret i64 %masked
+
+identity:
+ ret i64 %x
+}
+
+define i32 @xor_hoisted_not_i32(i32 %x, i32 %m, i1 zeroext %cond) {
+; CHECK-LABEL: xor_hoisted_not_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a2, .LBB32_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: .LBB32_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i32 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = xor i32 %a, %x
+ ret i32 %masked
+
+identity:
+ ret i32 %x
+}
+
+define i32 @xor_hoisted_not_i32_swapped(i32 %x, i32 %m, i1 zeroext %cond) {
+; CHECK-LABEL: xor_hoisted_not_i32_swapped:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a2, .LBB33_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: xor a0, a0, a1
+; CHECK-NEXT: .LBB33_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i32 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = xor i32 %x, %a
+ ret i32 %masked
+
+identity:
+ ret i32 %x
+}
+
+define i64 @xor_hoisted_not_i64(i64 %x, i64 %m, i1 zeroext %cond) {
+; CHECK-LABEL: xor_hoisted_not_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a4, .LBB34_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a3, a3
+; CHECK-NEXT: not a2, a2
+; CHECK-NEXT: xor a0, a2, a0
+; CHECK-NEXT: xor a1, a3, a1
+; CHECK-NEXT: .LBB34_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i64 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = xor i64 %a, %x
+ ret i64 %masked
+
+identity:
+ ret i64 %x
+}
+
+define i64 @xor_hoisted_not_i64_swapped(i64 %x, i64 %m, i1 zeroext %cond) {
+; CHECK-LABEL: xor_hoisted_not_i64_swapped:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a4, .LBB35_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a3, a3
+; CHECK-NEXT: not a2, a2
+; CHECK-NEXT: xor a0, a0, a2
+; CHECK-NEXT: xor a1, a1, a3
+; CHECK-NEXT: .LBB35_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i64 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = xor i64 %x, %a
+ ret i64 %masked
+
+identity:
+ ret i64 %x
+}
diff --git a/llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
index bf077364c9c7a..23b2c2d70a37a 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
@@ -554,3 +554,243 @@ define i1 @andn_snez_i64(i64 %a, i64 %b) nounwind {
%cmpeq = icmp ne i64 %and, %b
ret i1 %cmpeq
}
+
+define i32 @and_hoisted_not_i32(i32 %x, i32 %m, i1 zeroext %cond) {
+; CHECK-LABEL: and_hoisted_not_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a2, .LBB32_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: .LBB32_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i32 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = and i32 %a, %x
+ ret i32 %masked
+
+identity:
+ ret i32 %x
+}
+
+define i32 @and_hoisted_not_i32_swapped(i32 %x, i32 %m, i1 zeroext %cond) {
+; CHECK-LABEL: and_hoisted_not_i32_swapped:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a2, .LBB33_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: .LBB33_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i32 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = and i32 %x, %a
+ ret i32 %masked
+
+identity:
+ ret i32 %x
+}
+
+define i64 @and_hoisted_not_i64(i64 %x, i64 %m, i1 zeroext %cond) {
+; CHECK-LABEL: and_hoisted_not_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a2, .LBB34_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: .LBB34_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i64 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = and i64 %a, %x
+ ret i64 %masked
+
+identity:
+ ret i64 %x
+}
+
+define i64 @and_hoisted_not_i64_swapped(i64 %x, i64 %m, i1 zeroext %cond) {
+; CHECK-LABEL: and_hoisted_not_i64_swapped:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a2, .LBB35_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: .LBB35_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i64 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = and i64 %x, %a
+ ret i64 %masked
+
+identity:
+ ret i64 %x
+}
+
+define i32 @or_hoisted_not_i32(i32 %x, i32 %m, i1 zeroext %cond) {
+; CHECK-LABEL: or_hoisted_not_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a2, .LBB36_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: .LBB36_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i32 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = or i32 %a, %x
+ ret i32 %masked
+
+identity:
+ ret i32 %x
+}
+
+define i32 @or_hoisted_not_i32_swapped(i32 %x, i32 %m, i1 zeroext %cond) {
+; CHECK-LABEL: or_hoisted_not_i32_swapped:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a2, .LBB37_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: or a0, a0, a1
+; CHECK-NEXT: .LBB37_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i32 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = or i32 %x, %a
+ ret i32 %masked
+
+identity:
+ ret i32 %x
+}
+
+define i64 @or_hoisted_not_i64(i64 %x, i64 %m, i1 zeroext %cond) {
+; CHECK-LABEL: or_hoisted_not_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a2, .LBB38_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: .LBB38_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i64 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = or i64 %a, %x
+ ret i64 %masked
+
+identity:
+ ret i64 %x
+}
+
+define i64 @or_hoisted_not_i64_swapped(i64 %x, i64 %m, i1 zeroext %cond) {
+; CHECK-LABEL: or_hoisted_not_i64_swapped:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a2, .LBB39_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: or a0, a0, a1
+; CHECK-NEXT: .LBB39_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i64 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = or i64 %x, %a
+ ret i64 %masked
+
+identity:
+ ret i64 %x
+}
+
+define i32 @xor_hoisted_not_i32(i32 %x, i32 %m, i1 zeroext %cond) {
+; CHECK-LABEL: xor_hoisted_not_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a2, .LBB40_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: .LBB40_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i32 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = xor i32 %a, %x
+ ret i32 %masked
+
+identity:
+ ret i32 %x
+}
+
+define i32 @xor_hoisted_not_i32_swapped(i32 %x, i32 %m, i1 zeroext %cond) {
+; CHECK-LABEL: xor_hoisted_not_i32_swapped:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a2, .LBB41_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: xor a0, a0, a1
+; CHECK-NEXT: .LBB41_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i32 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = xor i32 %x, %a
+ ret i32 %masked
+
+identity:
+ ret i32 %x
+}
+
+define i64 @xor_hoisted_not_i64(i64 %x, i64 %m, i1 zeroext %cond) {
+; CHECK-LABEL: xor_hoisted_not_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a2, .LBB42_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: .LBB42_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i64 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = xor i64 %a, %x
+ ret i64 %masked
+
+identity:
+ ret i64 %x
+}
+
+define i64 @xor_hoisted_not_i64_swapped(i64 %x, i64 %m, i1 zeroext %cond) {
+; CHECK-LABEL: xor_hoisted_not_i64_swapped:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a2, .LBB43_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: xor a0, a0, a1
+; CHECK-NEXT: .LBB43_2: # %identity
+; CHECK-NEXT: ret
+ %a = xor i64 %m, -1
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = xor i64 %x, %a
+ ret i64 %masked
+
+identity:
+ ret i64 %x
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
index cf73dceaae306..96eead1c191f7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB-NOZBB,CHECK-ZVKB32
-; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB-NOZBB,CHECK-ZVKB64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB-ZBB,CHECK-ZVKB32
-; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB-ZBB,CHECK-ZVKB64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB-NOZBB,CHECK-ZVKB32,CHECK-ZVKB-NOZBB32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB-NOZBB,CHECK-ZVKB64,CHECK-ZVKB-NOZBB64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+zvkb,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB-ZBB,CHECK-ZVKB32,CHECK-ZVKB-ZBB32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+zvkb,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB-ZBB,CHECK-ZVKB64,CHECK-ZVKB-ZBB64
define <vscale x 1 x i8> @vandn_vv_nxv1i8(<vscale x 1 x i8> %x, <vscale x 1 x i8> %y) {
; CHECK-LABEL: vandn_vv_nxv1i8:
@@ -2109,3 +2109,376 @@ define <vscale x 1 x i16> @vand_vadd_vx_imm16(<vscale x 1 x i16> %x) {
%b = add <vscale x 1 x i16> %a, splat (i16 32767)
ret <vscale x 1 x i16> %b
}
+
+define <vscale x 1 x i8> @vand_vx_hoisted_not(<vscale x 1 x i8> %x, i8 %m, i1 zeroext %cond) {
+; CHECK-LABEL: vand_vx_hoisted_not:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a1, .LBB94_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a0, a0
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: .LBB94_2: # %identity
+; CHECK-NEXT: ret
+;
+; CHECK-ZVKB-LABEL: vand_vx_hoisted_not:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: beqz a1, .LBB94_2
+; CHECK-ZVKB-NEXT: # %bb.1: # %mask
+; CHECK-ZVKB-NEXT: not a0, a0
+; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-ZVKB-NEXT: vand.vx v8, v8, a0
+; CHECK-ZVKB-NEXT: .LBB94_2: # %identity
+; CHECK-ZVKB-NEXT: ret
+ %a = xor i8 %m, -1
+ %head = insertelement <vscale x 1 x i8> poison, i8 %a, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = and <vscale x 1 x i8> %splat, %x
+ ret <vscale x 1 x i8> %masked
+
+identity:
+ ret <vscale x 1 x i8> %x
+}
+
+define <vscale x 1 x i8> @vand_vx_hoisted_not_swapped(<vscale x 1 x i8> %x, i8 %m, i1 zeroext %cond) {
+; CHECK-LABEL: vand_vx_hoisted_not_swapped:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a1, .LBB95_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: not a0, a0
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: .LBB95_2: # %identity
+; CHECK-NEXT: ret
+;
+; CHECK-ZVKB-LABEL: vand_vx_hoisted_not_swapped:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: beqz a1, .LBB95_2
+; CHECK-ZVKB-NEXT: # %bb.1: # %mask
+; CHECK-ZVKB-NEXT: not a0, a0
+; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-ZVKB-NEXT: vand.vx v8, v8, a0
+; CHECK-ZVKB-NEXT: .LBB95_2: # %identity
+; CHECK-ZVKB-NEXT: ret
+ %a = xor i8 %m, -1
+ %head = insertelement <vscale x 1 x i8> poison, i8 %a, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = and <vscale x 1 x i8> %x, %splat
+ ret <vscale x 1 x i8> %masked
+
+identity:
+ ret <vscale x 1 x i8> %x
+}
+
+define <vscale x 1 x i8> @vand_vv_hoisted_not(<vscale x 1 x i8> %x, <vscale x 1 x i8> %m, i1 zeroext %cond) {
+; CHECK-LABEL: vand_vv_hoisted_not:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a0, .LBB96_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vnot.v v9, v9
+; CHECK-NEXT: vand.vv v8, v9, v8
+; CHECK-NEXT: .LBB96_2: # %identity
+; CHECK-NEXT: ret
+;
+; CHECK-ZVKB-LABEL: vand_vv_hoisted_not:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: beqz a0, .LBB96_2
+; CHECK-ZVKB-NEXT: # %bb.1: # %mask
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-ZVKB-NEXT: vnot.v v9, v9
+; CHECK-ZVKB-NEXT: vand.vv v8, v9, v8
+; CHECK-ZVKB-NEXT: .LBB96_2: # %identity
+; CHECK-ZVKB-NEXT: ret
+ %a = xor <vscale x 1 x i8> %m, splat (i8 -1)
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = and <vscale x 1 x i8> %a, %x
+ ret <vscale x 1 x i8> %masked
+
+identity:
+ ret <vscale x 1 x i8> %x
+}
+
+define <vscale x 1 x i8> @vand_vv_hoisted_not_swapped(<vscale x 1 x i8> %x, <vscale x 1 x i8> %m, i1 zeroext %cond) {
+; CHECK-LABEL: vand_vv_hoisted_not_swapped:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a0, .LBB97_2
+; CHECK-NEXT: # %bb.1: # %mask
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vnot.v v9, v9
+; CHECK-NEXT: vand.vv v8, v8, v9
+; CHECK-NEXT: .LBB97_2: # %identity
+; CHECK-NEXT: ret
+;
+; CHECK-ZVKB-LABEL: vand_vv_hoisted_not_swapped:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: beqz a0, .LBB97_2
+; CHECK-ZVKB-NEXT: # %bb.1: # %mask
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-ZVKB-NEXT: vnot.v v9, v9
+; CHECK-ZVKB-NEXT: vand.vv v8, v8, v9
+; CHECK-ZVKB-NEXT: .LBB97_2: # %identity
+; CHECK-ZVKB-NEXT: ret
+ %a = xor <vscale x 1 x i8> %m, splat (i8 -1)
+ br i1 %cond, label %mask, label %identity
+
+mask:
+ %masked = and <vscale x 1 x i8> %x, %a
+ ret <vscale x 1 x i8> %masked
+
+identity:
+ ret <vscale x 1 x i8> %x
+}
+
+declare i64 @llvm.vscale.i64()
+
+define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
+; CHECK-RV32-LABEL: vand_vx_loop_hoisted_not:
+; CHECK-RV32: # %bb.0: # %entry
+; CHECK-RV32-NEXT: csrr a4, vlenb
+; CHECK-RV32-NEXT: srli a3, a4, 3
+; CHECK-RV32-NEXT: li a2, 64
+; CHECK-RV32-NEXT: not a1, a1
+; CHECK-RV32-NEXT: bgeu a2, a3, .LBB98_2
+; CHECK-RV32-NEXT: # %bb.1:
+; CHECK-RV32-NEXT: li a3, 0
+; CHECK-RV32-NEXT: li a2, 0
+; CHECK-RV32-NEXT: j .LBB98_5
+; CHECK-RV32-NEXT: .LBB98_2: # %vector.ph
+; CHECK-RV32-NEXT: li a2, 0
+; CHECK-RV32-NEXT: slli a3, a3, 2
+; CHECK-RV32-NEXT: neg a3, a3
+; CHECK-RV32-NEXT: andi a3, a3, 256
+; CHECK-RV32-NEXT: srli a4, a4, 1
+; CHECK-RV32-NEXT: li a6, 0
+; CHECK-RV32-NEXT: li a5, 0
+; CHECK-RV32-NEXT: vsetvli a7, zero, e32, m2, ta, ma
+; CHECK-RV32-NEXT: .LBB98_3: # %vector.body
+; CHECK-RV32-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-RV32-NEXT: slli a7, a6, 2
+; CHECK-RV32-NEXT: add t0, a6, a4
+; CHECK-RV32-NEXT: add a7, a0, a7
+; CHECK-RV32-NEXT: vl2re32.v v8, (a7)
+; CHECK-RV32-NEXT: sltu a6, t0, a6
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: xor a6, t0, a3
+; CHECK-RV32-NEXT: vand.vx v8, v8, a1
+; CHECK-RV32-NEXT: or t1, a6, a5
+; CHECK-RV32-NEXT: vs2r.v v8, (a7)
+; CHECK-RV32-NEXT: mv a6, t0
+; CHECK-RV32-NEXT: bnez t1, .LBB98_3
+; CHECK-RV32-NEXT: # %bb.4: # %middle.block
+; CHECK-RV32-NEXT: bnez a3, .LBB98_6
+; CHECK-RV32-NEXT: .LBB98_5: # %for.body
+; CHECK-RV32-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-RV32-NEXT: slli a4, a3, 2
+; CHECK-RV32-NEXT: addi a3, a3, 1
+; CHECK-RV32-NEXT: add a4, a0, a4
+; CHECK-RV32-NEXT: lw a5, 0(a4)
+; CHECK-RV32-NEXT: seqz a6, a3
+; CHECK-RV32-NEXT: add a2, a2, a6
+; CHECK-RV32-NEXT: xori a6, a3, 256
+; CHECK-RV32-NEXT: and a5, a5, a1
+; CHECK-RV32-NEXT: or a6, a6, a2
+; CHECK-RV32-NEXT: sw a5, 0(a4)
+; CHECK-RV32-NEXT: bnez a6, .LBB98_5
+; CHECK-RV32-NEXT: .LBB98_6: # %for.cond.cleanup
+; CHECK-RV32-NEXT: ret
+;
+; CHECK-RV64-LABEL: vand_vx_loop_hoisted_not:
+; CHECK-RV64: # %bb.0: # %entry
+; CHECK-RV64-NEXT: csrr a4, vlenb
+; CHECK-RV64-NEXT: srli a2, a4, 3
+; CHECK-RV64-NEXT: li a3, 64
+; CHECK-RV64-NEXT: not a1, a1
+; CHECK-RV64-NEXT: bgeu a3, a2, .LBB98_2
+; CHECK-RV64-NEXT: # %bb.1:
+; CHECK-RV64-NEXT: li a2, 0
+; CHECK-RV64-NEXT: j .LBB98_5
+; CHECK-RV64-NEXT: .LBB98_2: # %vector.ph
+; CHECK-RV64-NEXT: slli a2, a2, 2
+; CHECK-RV64-NEXT: negw a2, a2
+; CHECK-RV64-NEXT: andi a2, a2, 256
+; CHECK-RV64-NEXT: srli a3, a4, 1
+; CHECK-RV64-NEXT: slli a4, a4, 1
+; CHECK-RV64-NEXT: mv a5, a0
+; CHECK-RV64-NEXT: mv a6, a2
+; CHECK-RV64-NEXT: vsetvli a7, zero, e32, m2, ta, ma
+; CHECK-RV64-NEXT: .LBB98_3: # %vector.body
+; CHECK-RV64-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-RV64-NEXT: vl2re32.v v8, (a5)
+; CHECK-RV64-NEXT: sub a6, a6, a3
+; CHECK-RV64-NEXT: vand.vx v8, v8, a1
+; CHECK-RV64-NEXT: vs2r.v v8, (a5)
+; CHECK-RV64-NEXT: add a5, a5, a4
+; CHECK-RV64-NEXT: bnez a6, .LBB98_3
+; CHECK-RV64-NEXT: # %bb.4: # %middle.block
+; CHECK-RV64-NEXT: bnez a2, .LBB98_7
+; CHECK-RV64-NEXT: .LBB98_5: # %for.body.preheader
+; CHECK-RV64-NEXT: slli a2, a2, 2
+; CHECK-RV64-NEXT: add a2, a0, a2
+; CHECK-RV64-NEXT: addi a0, a0, 1024
+; CHECK-RV64-NEXT: .LBB98_6: # %for.body
+; CHECK-RV64-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-RV64-NEXT: lw a3, 0(a2)
+; CHECK-RV64-NEXT: and a3, a3, a1
+; CHECK-RV64-NEXT: sw a3, 0(a2)
+; CHECK-RV64-NEXT: addi a2, a2, 4
+; CHECK-RV64-NEXT: bne a2, a0, .LBB98_6
+; CHECK-RV64-NEXT: .LBB98_7: # %for.cond.cleanup
+; CHECK-RV64-NEXT: ret
+;
+; CHECK-ZVKB32-LABEL: vand_vx_loop_hoisted_not:
+; CHECK-ZVKB32: # %bb.0: # %entry
+; CHECK-ZVKB32-NEXT: csrr a4, vlenb
+; CHECK-ZVKB32-NEXT: srli a3, a4, 3
+; CHECK-ZVKB32-NEXT: li a2, 64
+; CHECK-ZVKB32-NEXT: not a1, a1
+; CHECK-ZVKB32-NEXT: bgeu a2, a3, .LBB98_2
+; CHECK-ZVKB32-NEXT: # %bb.1:
+; CHECK-ZVKB32-NEXT: li a3, 0
+; CHECK-ZVKB32-NEXT: li a2, 0
+; CHECK-ZVKB32-NEXT: j .LBB98_5
+; CHECK-ZVKB32-NEXT: .LBB98_2: # %vector.ph
+; CHECK-ZVKB32-NEXT: li a2, 0
+; CHECK-ZVKB32-NEXT: slli a3, a3, 2
+; CHECK-ZVKB32-NEXT: neg a3, a3
+; CHECK-ZVKB32-NEXT: andi a3, a3, 256
+; CHECK-ZVKB32-NEXT: srli a4, a4, 1
+; CHECK-ZVKB32-NEXT: li a6, 0
+; CHECK-ZVKB32-NEXT: li a5, 0
+; CHECK-ZVKB32-NEXT: vsetvli a7, zero, e32, m2, ta, ma
+; CHECK-ZVKB32-NEXT: .LBB98_3: # %vector.body
+; CHECK-ZVKB32-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-ZVKB32-NEXT: slli a7, a6, 2
+; CHECK-ZVKB32-NEXT: add t0, a6, a4
+; CHECK-ZVKB32-NEXT: add a7, a0, a7
+; CHECK-ZVKB32-NEXT: vl2re32.v v8, (a7)
+; CHECK-ZVKB32-NEXT: sltu a6, t0, a6
+; CHECK-ZVKB32-NEXT: add a5, a5, a6
+; CHECK-ZVKB32-NEXT: xor a6, t0, a3
+; CHECK-ZVKB32-NEXT: vand.vx v8, v8, a1
+; CHECK-ZVKB32-NEXT: or t1, a6, a5
+; CHECK-ZVKB32-NEXT: vs2r.v v8, (a7)
+; CHECK-ZVKB32-NEXT: mv a6, t0
+; CHECK-ZVKB32-NEXT: bnez t1, .LBB98_3
+; CHECK-ZVKB32-NEXT: # %bb.4: # %middle.block
+; CHECK-ZVKB32-NEXT: bnez a3, .LBB98_6
+; CHECK-ZVKB32-NEXT: .LBB98_5: # %for.body
+; CHECK-ZVKB32-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-ZVKB32-NEXT: slli a4, a3, 2
+; CHECK-ZVKB32-NEXT: addi a3, a3, 1
+; CHECK-ZVKB32-NEXT: add a4, a0, a4
+; CHECK-ZVKB32-NEXT: lw a5, 0(a4)
+; CHECK-ZVKB32-NEXT: seqz a6, a3
+; CHECK-ZVKB32-NEXT: add a2, a2, a6
+; CHECK-ZVKB32-NEXT: xori a6, a3, 256
+; CHECK-ZVKB32-NEXT: and a5, a5, a1
+; CHECK-ZVKB32-NEXT: or a6, a6, a2
+; CHECK-ZVKB32-NEXT: sw a5, 0(a4)
+; CHECK-ZVKB32-NEXT: bnez a6, .LBB98_5
+; CHECK-ZVKB32-NEXT: .LBB98_6: # %for.cond.cleanup
+; CHECK-ZVKB32-NEXT: ret
+;
+; CHECK-ZVKB64-LABEL: vand_vx_loop_hoisted_not:
+; CHECK-ZVKB64: # %bb.0: # %entry
+; CHECK-ZVKB64-NEXT: csrr a4, vlenb
+; CHECK-ZVKB64-NEXT: srli a2, a4, 3
+; CHECK-ZVKB64-NEXT: li a3, 64
+; CHECK-ZVKB64-NEXT: not a1, a1
+; CHECK-ZVKB64-NEXT: bgeu a3, a2, .LBB98_2
+; CHECK-ZVKB64-NEXT: # %bb.1:
+; CHECK-ZVKB64-NEXT: li a2, 0
+; CHECK-ZVKB64-NEXT: j .LBB98_5
+; CHECK-ZVKB64-NEXT: .LBB98_2: # %vector.ph
+; CHECK-ZVKB64-NEXT: slli a2, a2, 2
+; CHECK-ZVKB64-NEXT: negw a2, a2
+; CHECK-ZVKB64-NEXT: andi a2, a2, 256
+; CHECK-ZVKB64-NEXT: srli a3, a4, 1
+; CHECK-ZVKB64-NEXT: slli a4, a4, 1
+; CHECK-ZVKB64-NEXT: mv a5, a0
+; CHECK-ZVKB64-NEXT: mv a6, a2
+; CHECK-ZVKB64-NEXT: vsetvli a7, zero, e32, m2, ta, ma
+; CHECK-ZVKB64-NEXT: .LBB98_3: # %vector.body
+; CHECK-ZVKB64-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-ZVKB64-NEXT: vl2re32.v v8, (a5)
+; CHECK-ZVKB64-NEXT: sub a6, a6, a3
+; CHECK-ZVKB64-NEXT: vand.vx v8, v8, a1
+; CHECK-ZVKB64-NEXT: vs2r.v v8, (a5)
+; CHECK-ZVKB64-NEXT: add a5, a5, a4
+; CHECK-ZVKB64-NEXT: bnez a6, .LBB98_3
+; CHECK-ZVKB64-NEXT: # %bb.4: # %middle.block
+; CHECK-ZVKB64-NEXT: bnez a2, .LBB98_7
+; CHECK-ZVKB64-NEXT: .LBB98_5: # %for.body.preheader
+; CHECK-ZVKB64-NEXT: slli a2, a2, 2
+; CHECK-ZVKB64-NEXT: add a2, a0, a2
+; CHECK-ZVKB64-NEXT: addi a0, a0, 1024
+; CHECK-ZVKB64-NEXT: .LBB98_6: # %for.body
+; CHECK-ZVKB64-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-ZVKB64-NEXT: lw a3, 0(a2)
+; CHECK-ZVKB64-NEXT: and a3, a3, a1
+; CHECK-ZVKB64-NEXT: sw a3, 0(a2)
+; CHECK-ZVKB64-NEXT: addi a2, a2, 4
+; CHECK-ZVKB64-NEXT: bne a2, a0, .LBB98_6
+; CHECK-ZVKB64-NEXT: .LBB98_7: # %for.cond.cleanup
+; CHECK-ZVKB64-NEXT: ret
+entry:
+ %not = xor i32 %mask, -1
+ %vscale = tail call i64 @llvm.vscale.i64()
+ %min.iters.check = icmp samesign ugt i64 %vscale, 64
+ br i1 %min.iters.check, label %for.body.preheader, label %vector.ph
+
+vector.ph:
+ %1 = tail call i64 @llvm.vscale.i64()
+ %.neg = mul nuw nsw i64 %1, 508
+ %n.vec = and i64 %.neg, 256
+ %2 = tail call i64 @llvm.vscale.i64()
+ %3 = shl nuw nsw i64 %2, 2
+ %broadcast.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %not, i64 0
+ %broadcast.splat = shufflevector <vscale x 4 x i32> %broadcast.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+ br label %vector.body
+
+vector.body:
+ %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+ %4 = getelementptr inbounds nuw i32, ptr %a, i64 %index
+ %wide.load = load <vscale x 4 x i32>, ptr %4, align 4
+ %5 = and <vscale x 4 x i32> %wide.load, %broadcast.splat
+ store <vscale x 4 x i32> %5, ptr %4, align 4
+ %index.next = add nuw i64 %index, %3
+ %6 = icmp eq i64 %index.next, %n.vec
+ br i1 %6, label %middle.block, label %vector.body
+
+middle.block:
+ %cmp.n.not = icmp eq i64 %n.vec, 0
+ br i1 %cmp.n.not, label %for.body.preheader, label %for.cond.cleanup
+
+for.body.preheader:
+ %indvars.iv.ph = phi i64 [ 0, %entry ], [ %n.vec, %middle.block ]
+ br label %for.body
+
+for.cond.cleanup:
+ ret void
+
+for.body:
+ %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ %indvars.iv.ph, %for.body.preheader ]
+ %arrayidx = getelementptr inbounds nuw i32, ptr %a, i64 %indvars.iv
+ %7 = load i32, ptr %arrayidx, align 4
+ %and = and i32 %7, %not
+ store i32 %and, ptr %arrayidx, align 4
+ %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+ %exitcond.not = icmp eq i64 %indvars.iv.next, 256
+ br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
+}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-ZVKB-NOZBB32: {{.*}}
+; CHECK-ZVKB-NOZBB64: {{.*}}
+; CHECK-ZVKB-ZBB32: {{.*}}
+; CHECK-ZVKB-ZBB64: {{.*}}
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